参数资料
型号: SED1278D0G
元件分类: 显示控制器
英文描述: 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC
封装: ALUMINUM PAD, DIE
文件页数: 36/39页
文件大小: 207K
代理商: SED1278D0G
9–6
EPSON
SED1278
4.
Input/Output terminal configuration
VDD
Applicable terminal
DBO to DB7
Internal
VSS
INSTRUCTION DESCRIPTION
Instruction Summary
* Don’t care
Instruction
Code
Description
Cycle Time
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(max.)
Clear Display
0
0000
1
Clears all display data and sets DDRAM
410 clocks
address 0 in the address counter.
Set DDRAM address 0 in the address
Return Home
0
0000
0001
*
counter. Also returns any shifted data to
410 clocks
home. The contents of DDRAM remain
unchanged.
Specifies the direction in which the cursor
Entry Mode Set
0
0000
001
I/D
S
moves and whether the display is to be
10 clocks
shifted or not, when data is writen to or read
from memory
Sets all display on/off (D) cursor on/off (C),
Display ON/OFF
0
0000
01
D
C
B
and character blinking in the cursor position
10 clocks
(B).
Cursor or
0
0000
1
S/C R/L
*
Moves the cursor and shifts the display
10 clocks
Display Shift
without changing the contents of DDRAM.
Sets the interface data length (IF), number of
System Set
0
0001
IF
N
F
*
characters to be displayed (N), and character
10 clocks
font (F).
Set CGRAM
0
001
ACG
Set CGRAM addresses, followed by
10 clocks
Address
transfer of CGRAM data.
Set DDRAM
00
1
ADD
Sets DDRAM address, followed by
10 clocks
Address
transfer of DDRAM data.
Read Busy Flag
Reads the busy flag (BF) which indicates
and Address
01
BF
ACC
internal operation and the contents of the
0
address counter.
Write Data to
1
0
Write Data
Writes data to DDRAM or CGRAM.
10 clocks
CG or DDRAM
Read Data from
1
Read Data
Reads data from DDRAM or CGRAM.
10 clocks
CG or DDRAM
相关PDF资料
PDF描述
SED1278F0H 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP80
SED1278D 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC80
SED1278F 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP80
SED1278F0G 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, PQFP80
SED1278D0B 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC80
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