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参数资料
| 型号： | SED1345F0A |
| 元件分类： | 显示控制器 |
| 英文描述： | 640 X 480 DOTS CRT TO LCD CONV DSPL CTLR, PQFP80 |
| 封装： | QFP-80 |
| 文件页数： | 10/12页 |
| 文件大小： | 45K |
| 代理商： | SED1345F0A |
191
° Y Driver
(VDD = 5V
±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
Symbol
Condition
Min*
Typ
Max
Unit
YD Setup Time
tSUYD1
S0 = “H”
142t1–100
——
ns
before LP, YSCL
S5 = “H”
S0 = “L”
302t1–100
YD Hold Time
thYD1
S0 = “H”
18t1–100
——
ns
after LP, YSCL
S0 = “L”
18t1–100
S0 = “H”
S6 = “H” 141.5t1–100
YD Setup Time
tSUYD2
S6 = “L”
141t1–100
——
ns
before LP, YSCL
S0 = “L”
S6 = “H” 301.5t1–100
S5 = “L”
S6 = “L”
301t1–100
S0 = “H”
S6 = “H”
17.5t1–100
YD Hold Time
tHYD2
S6 = “L”
17t1–100
——
ns
after LP, YSCL
S0 = “L”
S6 = “H”
17.5t1–100
S6 = “L”
17t1–100
t1=2tCCK (tCCK = dot clock cycle)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
CK Cycle Time
tCCK
33
—
ns
CK “H” Pulse Width
tWCKW
12
—
ns
CK “L” Pulse Width
tWCKL
12
—
ns
Input Rise Time
tr2
——
5
ns
Input Fall Time
tf2
——
5
ns
VD Setup Time Before CK
tSUVD
16
—
ns
VD Hold Time After CK
tHVD
2—
—
ns
CK Setup Time Before HSC
tSUCK
20
—
ns
CK Hold Time After HSC
tHCK
0—
—
ns
HSC Setup Time Before VSC
tSUVH
80
—
ns
HSC Hold Time After VSC
tHVM
0—
—
ns
Active Pulse Width HSC
tWH1
8tCCK
——
ns
Non-Active Pulse Width HSC
tWH2
64tCCK
——
ns
(VDD = 5V
±5%, VSS = 0V, Ta = 0 to 70°C)
SED1345
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