- 您现在的位置：买卖IC网 > PDF目录98079 > SED1351F0A DOT MAT LCD DSPL CTLR, PQFP100 PDF资料下载
参数资料
| 型号： | SED1351F0A |
| 元件分类： | 显示控制器 |
| 英文描述： | DOT MAT LCD DSPL CTLR, PQFP100 |
| 封装： | QFP5-100 |
| 文件页数： | 3/18页 |
| 文件大小： | 80K |
| 代理商： | SED1351F0A |
207
SED1351
Pin Name
Type
F0A
FLB
Drv
Description
Pin No.
DB0 to DB15
I/O
30 to 45
28 to 43
These pins are interfaced with the MPU data bus.
When using an 8-bit MPU, connect DB8 to DB15 to
VDD.
AB0 to AB15
I
14 to 29
12 to 27
These pins are interfaced with the MPU address bus.
If multiplexed address signals are used, connect them
via latch circuits. A control register is selected by AB0
to AB3. Correspondence of the MPU address bus to
the VRAM address bus is such that ABi = VAi (where
i is a pin number).
BHE
I
13
11
This signal is a bus high enable signal where a 16-bit
MPU is used. It goes “L” (low) when an odd address is
encountered. When using an 8-bit MPU configuration,
connect the BHE pin to VDD.
IOCS
I
3
1
This pin selects a control register contained in the
SED1351. It is “L” active, and must be assigned to
MPU I/O space.
IOWR
I
4
2
This signal is used for writing data into a control
register contained in the SED1351. It is “L” active, and
must go “L” when it encounters an OUT instruction
from the MPU.
IORD
I
5
3
This signal is used for reading data from a control
register contained in the SED1351. It is “L” active, and
must go “L” when it encounters an IN instruction from
the MPU.
MEMCS
I
6
4
This signal is used for selecting VRAM. It is “L” active,
and must be assigned to MPU memory space.
MEMWR
I
7
5
This signal is used for writing data to the VRAM. It is “L”
active, and must go “L” when it encounters a memory
write instruction from the MPU.
MEMRD
I
8
6
This signal is used for reading data from the VRAM. It
is “L” active, and must go “L” when it encounters a
memory read instruction from the MPU.
READY
O
9
7
This signal requests the MPU to wait. It goes “L” by the
falling edge of IOCS or MEMCS. It goes “H” by the
rising edge of MPUCLK after completion of the
SED1351 internal processing. Since READY is not a
tri-state pin, it needed not be pulled up and must be
connected directly to the READY (WAIT) terminal of
the MPU.
MPUCLK
I
10
8
This pin accepts an MPU clock. The MPU wait state is
cleared by the rising edge of MPUCLK.
MPUSEL
I
12
10
This signal is connected to either VDD or VSS for
selection of an MPU.
MPUSEL = VSS 8-bit MPU (e.g., Z80, V20, i8088)
MPUSEL = VDD 16-bit MPU (e.g., V30, i8086)
RESET
I
11
9
The MPU reset signal comes to this pin. It is “H” active,
and initializes a control register.
s PIN DESCRIPTION
1. System Connector Terminals (at MPU)
相关PDF资料 |
PDF描述 |
|---|---|
| SED1352 | 640 X 480 PIXELS DOT MAT LCD DSPL CTLR, PQFP100 |
| SH1475IMLTRT | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC36 |
| SH2165-FGT | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP64 |
| SH3001IMLTRT | REAL TIME CLOCK, QCC16 |
| SH3001IMLTR | REAL TIME CLOCK, QCC16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SED1352 | 制造商:EPSON 制造商全称:EPSON 功能描述:Document Number: X16B-Q-001-06 |
| SED1353 | 制造商:EPSON 制造商全称:EPSON 功能描述:SED1353 GRAPHICS LCD CONTROLLER |
| SED1353D0A | 制造商:EPSON 制造商全称:EPSON 功能描述:LCD Controller ICs |
| SED1353F0A | 制造商:EPSON 制造商全称:EPSON 功能描述:LCD Controller ICs |
| SED1353F1A | 制造商:EPSON 制造商全称:EPSON 功能描述:LCD Controller ICs |
发布紧急采购，3分钟左右您将得到回复。