参数资料
型号: SFC3.3-4.TF
元件分类: TVS二极管 - 瞬态电压抑制
英文描述: 150 W, UNIDIRECTIONAL, 4 ELEMENT, SILICON, TVS DIODE, MO-211BB
封装: FLIP CHIP, CSP-6
文件页数: 1/7页
文件大小: 236K
代理商: SFC3.3-4.TF
PROTECTION PRODUCTS
1
www.semtech.com
PROTECTION PRODUCTS
SFC3.3-4
Low Voltage ChipClampΤΜ
ΤΜ
Flip Chip TVS Diode Array
Description
Features
Device Dimensions
Schematic & PIN Configuration
Revision 11/18/03
The SFC3.3-4 is a quad flip chip TVS diode array. They
are state-of-the-art devices that utilize solid-state EPD
TVS technology for superior clamping performance and
DC electrical characteristics. The SFC series TVS
diodes are designed to protect sensitive semiconduc-
tor components from damage or latch-up due to
electrostatic discharge (ESD) and other voltage in-
duced transient events.
The SFC3.3-4 is a 6-bump, 0.5mm pitch flip chip array
with a 3x2 bump grid. It measures approximately 1.5
by 1.0 mm. It has a very low profile of < 0.65 mm.
This is a crucial specification for many portable applica-
tions. Each device will protect up to four data or I/O
lines. The CSP design results in lower inductance,
virtually eliminating voltage overshoot due to leads and
interconnecting bond wires.
The devices are constructed using Semtech’s propri-
etary EPD process technology. The EPD process pro-
vides low standoff voltages with significant reductions
in leakage currents and capacitance over silicon-
avalanche diode processes.
They may be used to meet the ESD immunity require-
ments of IEC 61000-4-2, Level 4 (±15kV air, ±8kV
contact discharge).
Applications
Mechanical Characteristics
Cell Phone Handsets and Accessories
Personal Digital Assistants (PDA’s)
Notebook and Hand Held Computers
Portable Instrumentation
Pagers
Smart Cards
MP3 Players
150 Watts peak pulse power (tp = 8/20s)
Transient protection for data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 12A (8/20s)
Small chip scale package requires less board space
Low profile (< 0.65mm)
No need for underfill material
Protects four I/O or data lines
Low clamping voltage
Working voltage: 3.3V
Solid-state EPD TVS technology
JEDEC MO-211, Variation BB, 0.50 mm Pitch Chip
Scale Package (CSP)
Marking : Marking Code
Packaging : Tape and Reel
SFC3.3-4 Maximum Dimensions (mm)
3 x 2 Grid Flip Chip TVS (Bottom View)
12
3
A
B
相关PDF资料
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