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参数资料
| 型号： | SFPA2048Q1BO2TO-I-MS-223-STD |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 13/76页 |
| 文件大小： | 0K |
| 描述： | FLASH SSD SMART UDMA 2.5" 2GB |
| 视频文件： | Swissbit Manufacturing Overview |
| RoHS指令信息： | Environment Protection Declaration |
| 标准包装： | 4 |
| 系列： | P-120 |
| 存储容量： | 2GB |
| 存储器类型： | FLASH |
| 其它名称： | 1052-1023 |
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1.
2.
3.
4.
The maximum load on – IOCS16 is 1 LSTTL with a 50pF total load.
t 0 is the minimum total cycle time, t 2 is the minimum command active time, and t 2i is the minimum command recovery time
or command inactive time. The actual cycle time equals the sum of the actual command inactive time. The three timing
requirements of t0, t 2 , and t 2i have to be met. The requirement is greater than the sum of t 2 and t 2i . This means a host
implementation can ensure that t0 is equal to or greater than the value reported in the devices identify drive
implementation should support any legal host implementation.
This parameter specifies the time from the falling edge of – IORD to the moment when the drive (tri-state).
t 7 and t 8 apply only to modes 0, 1 and 2. The – IOCS16 signal is not valid for other modes.
6.2 MDMA Mode
Figure 2: True IDE Multi-Word DMA Mode Read/Write waveforms
– DMARQ
– DMACK
Table 20: True IDE Multi-Word DMA Mode Read/Write timing
t 0
t D
t KR
t KW
Parameter
Cycle time (min)
-IORD / -IOWR asserted width (min)
-IORD data access (max)
-IORD data hold (min)
-IORD/-IOWR data setup (min)
-IOWR data hold (min)
DMACK to – IORD/-IOWR setup (min)
-IORD / -IOWR to – DMACK hold (min)
-IORD Low width (min)
-IOWR Low width (min)
-IORD to DMARQ delay (max)
-IOWR to DMARQ delay (max)
CS(1:0) valid to – IORD / -IOWR
CS(1:0) hold
Symbol
(1)
(1)
t E
t F
t G
t H
t I
t J
(1)
(1)
t LR
t LW
t M
t N
Mode 0
(ns)
480
215
150
5
100
20
0
20
50
215
120
40
50
15
1
(ns)
150
80
60
5
30
15
0
5
50
50
40
40
30
10
2
(ns)
120
70
50
5
20
10
0
5
25
25
35
35
25
10
-DMACK t Z 20 25 25
1. t 0 is the minimum total cycle time. T D is the minimum command active time. T KR and t KW are the minimum command
recovery time or command inactive time for input and output cycles, respectively. The actual cycle time is the sum of the
actual command active time and the actual command inactive time. The timing requirements of t 0 , t D , t KR , and t KW must be
respected. T 0 is higher than t D + t KR or t D + t KW , for input and output cycles respectively. This means the host can lengthen
either t D or t KR /t KW , or both, to ensure that t 0 is equal to or higher than the value reported in the devices identify device
data. A Drive implementation shall support any legal host implementation.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
P-120_data_sheet_PA-QxBO_Rev100.doc
Page 13 of 76
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