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参数资料
| 型号： | SG-8002JC25.0000M-PCCL0:ROHS |
| 厂商： | EPSON TOYOCOM CORP |
| 元件分类： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 25 MHz, CMOS OUTPUT |
| 封装： | ROHS COMPLIANT, PLASTIC PACKAGE-4 |
| 文件页数： | 3/4页 |
| 文件大小： | 813K |
http://www.epsontoyocom.co.jp
Crystal oscillator
Epson Toyocom
SG / HG-8002 series_ Jitter specifications and characteristics chart
■PLL-PLL connection
Because we use a PLL technology, there are a few cases that the jitter value will increase when SG-8002 is connected to another
PLL-oscillator.
In our experience, we are unable to recommend these products for the applications such as telecom carrier use or analog video
clock use. Please be careful checking in advance for these application (Jitter specification is Max.250 ps/CL=15 pF)
Jitter Specifications
Model
Supply
Voltage
Jitter Item
Specifications
Remarks
150 ps Max.
33 MHz
≤ f0 ≤ 125 MHz, L_CMOS=15 pF
Cycle to cycle
200 ps Max.
1.0 MHz
≤ f0 < 33 MHz, L_CMOS=15 pF
200 ps Max.
33 MHz
≤ f0 ≤ 125 MHz, L_CMOS=15 pF
PT / PH
ST / SH
5.0 V
±0.5 V
Peak to peak
250 ps Max.
1.0 MHz
≤ f0 < 33 MHz, L_CMOS=15 pF
Cycle to cycle
200 ps Max.
1.0 MHz
≤ f0 ≤ 125 MHz, L_CMOS=15 pF
SC / PC
3.3 V
±0.3 V
Peak to peak
250 ps Max.
1.0 MHz
≤ f0 ≤ 125 MHz, L_CMOS=15 pF
■Remarks on noise management for power supply line
We do not recommend inserting filters or other devices in the power supply line as the counter measure of EMI noise reduction.
This device insertion might cause high-frequency impedance high in the power supply line and it affects oscillator stable drive.
When this measure is required, please evaluate circuitry and device behavior in the circuit and verify that it will not affect oscillation.
Start up time (0 % VCC to 90 % VCC) of power source should be more than 150
s.
■SG-8002 series Characteristics chart
VCC=5.0 V
25 pF
Frequency(MHz)
0
Current consumption (VCC=5.0V)
20
40
60
80 100 120 140
10
20
30
40
50
ICC
(m
A
)
Frequency(MHz)
0
Disable Current (VCC=5.0V)
20
40
60
80 100 120 140
10
20
30
40
50
I_di
s
(m
A
)
VCC (V)
I_s
td
(
A)
2.5
Stand-by Current
3.0 3.5 4.0 4.5 5.0
5.5 6.0
10
20
30
40
50
Frequency(MHz)
0
Symmetry 5.0V TTL Level
20
40
60
80 100 120 140
40
45
50
55
60
S
ym
m
et
ry
(%
)
0
Symmetry 3.3 V CMOS Level
20
40
60
80 100 120 140
40
45
50
55
60
Frequency(MHz)
S
ym
m
et
ry
(%
)
0
Symmetry 5.0 V CMOS Level
20
40
60
80 100 120 140
40
45
50
55
60
Frequency(MHz)
S
ym
m
et
ry
(%
)
0
Frequency(MHz)
Output load vs. Additional Current consumption
20
40
60
80 100 120 140
2
4
6
8
10
12
14
16
18
20
2.5
VCC (V)
Voltage coefficient [ VCC vs I_dis,I_std ]
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0.2
0.4
0.6
Time
s
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Ri
se
ti
m
e(
ns)
10
Output Rise time (CMOS Level)
15 20 25 30 35 40 45
1.0
1.5
2.0
3.0
2.5
Load capacitance (pF)
50 55
Output Fall time (CMOS Level)
3.0
10 15 20 25 30 35 40 45
1.0
1.5
2.0
2.5
Load capacitance (pF)
Fa
llTime
(ns
)
50 55
10
Output Fall time (TTL Level)
15
20
25
30
1.0
1.5
2.0
Load capacitance (pF)
Fa
llTime
(
ns
)
Output Rise time (TTL Level)
10
15
20
25
30
1.0
1.5
2.0
Load capacitance (pF)
Ri
se
T
im
e
(n
s)
15 pF
50 pF
15 pF
30 pF
25 pF
15 pF
I_dis(Va)=Times(Va)×I_dis(5.0V)
I_std(Va)=Times(Va)×I_std(5.0V)
25 pF
15 pF
50 pF
30 pF
5.0 V
5.5 V
4.5 V
3.3 V
3.6 V
3.0 V
3.3 V
3.6 V
3.0 V
5.0 V
5.5 V
4.5 V
5.0 V
5.5 V
4.5 V
5.0 V
5.5 V
4.5 V
2.7 V
25 pF
A
ddi
tional
V
al
ue
(m
A
)
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