参数资料
| 型号： | SG1577DY |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 11/14页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST PWM VM 20-DIP |
| 标准包装： | 22 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 352kHz |
| 占空比： | 95% |
| 电源电压： | 8 V ~ 15 V |
| 降压： | 是 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-DIP（0.300"，7.62mm） |
| 包装： | 管件 |
Type II Compensation Design
(for Output Capacitors with High ESR)
SG1577 is a voltage-mode controller; the control loop is
a single voltage feedback path, including an error
amplifier and PWM comparator, as shown in Figure 24.
To achieve fast transient response and accurate output
2. Compensation Frequency Equations
The compensation network consists of the error
amplifier and the impedance networks Z C and Z f , as
Figure 24 shows.
regulation, an adequate compensator
design is
necessary. A stable control loop has a 0 dB gain
crossing with -20 dB/decade slope and a phase margin
greater than 45°.
Figure 25. Compensation Loop
f P 1 = 0
f Z 1 =
f P 2 =
1
2 π × R 2 × C 2
1
2 π × R 2 × ( C 1 // C 2 )
(6)
Figure 24. Closed Loop
1. Modulator Frequency Equations
The modulator transfer function is the small-signal
transfer function of V OUT/ V E/A . This transfer function is
dominated by a DC gain and the output filter (L O and C O )
with a double-pole frequency at f LC and a zero at FESR.
The DC gain of the modulator is the input voltage (V IN )
divided by the peak-to-peak oscillator voltage
V RAMP (=1.6 V). The first step is to calculate the complex
conjugate poles contributed by the LC output filter. The
output LC filter introduces a double pole,
-40 dB / decade gain slope above its corner resonant
frequency, and a total phase lag of 180°. The resonant
frequency of the LC filter expressed as:
Figure 26 shows the DC-DC converter gain vs.
frequency. The compensation gain uses external
impedance networks ZC and Zf to provide a stable,
high-bandwidth loop.
High crossover frequency is desirable for fast transient
response, but often jeopardizes the system stability. To
cancel one of the LC filter poles, place the zero before
the LC filter resonant frequency. Place the zero at 75%
of the LC filter resonant frequency. Crossover frequency
should be higher than the ESR zero, but less than 1/5 of
the switching frequency. The second pole should be
placed at half the switching frequency.
f P(LC) =
1
2 π × L O × C O
(4)
The next step of compensation design is to calculate the
ESR zero. The ESR zero is contributed by the ESR
associated with the output capacitance. Note that this
requires that the output capacitor should have enough
ESR to satisfy stability requirements. The ESR zero of
the output capacitor is expressed as:
f Z ( ESR ) =
1
2 π × C O × ESR
(5)
Figure 26. Bode Plot
? 2009 Fairchild Semiconductor Corporation
SG1577 ? Rev. 1.0.6
11
www.fairchildsemi.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SG1577DZ | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Dual Synchronous DC/DC Controller |
| SG1577SY | 功能描述:DC/DC 开关控制器 Dual Sync DC/DC Controller RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| SG1577SY_12 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Dual Synchronous DC/DC Controller |
| SG1577SZ | 功能描述:DC/DC 开关控制器 Dual Synchronous DC/DC Controller RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| SG15A | 制造商:BILIN 制造商全称:Galaxy Semi-Conductor Holdings Limited 功能描述:FAST RECOVERY RECTIFIERS |
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