参数资料
型号: SG1577SZ
厂商: Fairchild Semiconductor
文件页数: 12/14页
文件大小: 0K
描述: IC REG CTRLR BST PWM VM 20-SOP
标准包装: 1
PWM 型: 电压模式
输出数: 2
频率 - 最大: 352kHz
占空比: 95%
电源电压: 8 V ~ 15 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
包装: 标准包装
产品目录页面: 1222 (CN2011-ZH PDF)
其它名称: SG1577SZDKR
Layout Considerations
Layout is important in high-frequency switching converter
design. If designed improperly, PCB can radiate
components close to their pins with a local, clear
GND connection or directly to the ground plane.
excessive noise and contribute to converter instability.
Place the PWM power stage components first. Mount all
the power components and connections in the top layer
with wide copper areas. The MOSFETs of buck,
inductor, and output capacitor should be as close to
each other as possible to reduce the radiation of EMI
due to the high-frequency current loop. If the output
capacitors are placed in parallel to reduce the ESR of
7
8
Place the bootstrap capacitor near the BSTx and
CLNx pins.
The resistor on the RT pin should be near this pin
and the GND return should be short and kept away
from the noisy MOSFET’s GND (which is short
together with IC’s PGND pin to GND plane on back
side of PCB).
capacitor, equal sharing ripple current should be
considered. Place the input capacitor near the drain of
high-side MOSFET. In multi-layer PCB, use one layer as
power ground and have a separate control signal ground
as the reference for all signals. To avoid the signal
ground being affected by noise and have best load
regulation, it should be connected to the ground terminal
of output.
Follow the below guidelines for best performance:
1 A two-layer printed circuit board is recommended.
2 Use the bottom layer of the PCB as a ground plane
and make all critical component ground connections
through vias to this layer.
9 Place the compensation components close to the
INx and COMPx pins.
10 The feedback resistors for both regulators should
be located as close as possible to the relevant INx
pin with vias tied straight to the ground plane as
required.
11 Minimize the length of the connections between the
input capacitors, CIN, and the power switchers
(MOSFETs) by placing them nearby.
12 Position both the ceramic and bulk input capacitors
as close to the upper MOSFET drain as possible
and make the GND returns (from the source of
lower MOSFET to V IN capacitor GND) short.
3
4
5
6
Keep the metal running from the CLNx terminal to
the output inductor short.
Use copper-filled polygons on the top (and bottom,
if two-layer PCB) circuit layers for the CLN node.
The small-signal wiring traces from the DLx and
DHx pins to the MOSFET gates should be kept
short and wide enough to easily handle the several
amps of drive current.
The critical, small-signal components include any
bypass capacitors (SMD-type of capacitors applied
at VCC and SSx/ENB pins), feedback components
(resistor divider), and compensation components
(between INx and COMPx pins). Position those
13 Position the output inductor and output capacitors
between the upper MOSFET and lower MOSFET
and the load.
14 AGND should be on the clearer plane and kept
away from the noisy MOSFET GND.
15 PGND should be short, together with MOSFET
GND, then through vias to GND plane on the
bottom of PCB.
16 Prevent spike happen on CLN pin a proper snubber
circuit for CLN and GND is recommend.
? 2009 Fairchild Semiconductor Corporation
SG1577 ? Rev. 1.0.6
12
www.fairchildsemi.com
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