参数资料
型号: SG3525ADWG
厂商: ON Semiconductor
文件页数: 7/10页
文件大小: 0K
描述: IC REG CTRLR PWM VM 16-SOIC
产品变化通告: Product Discontinuation 27/Jan/2012
标准包装: 47
PWM 型: 电压模式
输出数: 2
频率 - 最大: 400kHz
占空比: 49%
电源电压: 8 V ~ 35 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
包装: 管件
SG3525A
Q5
V CC
Q7
13
V C
Q4
Q9
Q10
5.0k
V ref
Q8
11, 14
Q11 Output
Q6
2.0k
Q1
Q2
Q3
Q6 Omitted
in SG3527A
5.0k
Clock
F/F
10k
10k
PWM
Figure 9. Output Circuit
(1/2 Circuit Shown)
+ V supply
R1
Q1
R2
To Output Filter
+V supply
R1
13
C1
V C
13
A
11
V C A
SG3525A
11
R2
C2
Q1
T1
SG3525A
GND
12
B
14
B
GND
12
14
R3
Q2
For single?ended supplies, the driver outputs are grounded.
The V C terminal is switched to ground by the totem?pole
source transistors on alternate oscillator cycles.
Figure 10. Single?Ended Supply
In conventional push?pull bipolar designs, forward base drive is
controlled by R1?R3. Rapid turn?off times for the power devices
are achieved with speed?up capacitors C1 and C2.
Figure 11. Push?Pull Configuration
+ V supply
R1
+V supply
Q1
13
V C A
11
Q1
T1
13
V C A
11
T1
R1
T2
C1
SG3525A
GND B
14
Q2
SG3525A
GND B
14
Q2
C2
12
12
R2
The low source impedance of the output drivers provides
rapid charging of power FET input capacitance while
minimizing external components.
Figure 12. Driving Power FETS
http://onsemi.com
7
Low power transformers can be driven directly by the SG3525A.
Automatic reset occurs during deadtime, when both ends of the
primary winding are switched to ground.
Figure 13. Driving Transformers in a
Half?Bridge Configuration
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