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参数资料
| 型号： | SG500DYB |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | XO, clock |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封装： | 0.209 INCH, SSOP-28 |
| 文件页数： | 2/7页 |
| 文件大小： | 92K |
| 代理商： | SG500DYB |
SG500
Low Jitter Spectrum Clock Generator for PowerPC Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.2.1
9/18/98
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 2 of 7
PIN DESCRIPTION
Pin Number
Pin Name
PWR
I/O
Description
2
XIN
VDD
I
These pins form an on-chip reference oscillator when
connected to terminals of an external parallel resonant
crystal (nominally 14.318 MHz). Xin may also serve as
input for an externally generated reference signal. If the
external input is used, Pin 3 is left unconnected.
3
XOUT
VDD
O
18
PCIF
VDDP
O
66.6 Mhz FAST PCI clock rising edge synchronized to the
CPU clock.
21
PCI
VDDP
O
33.3 Mhz PCI clock rising edge synchronized to the CPU
clock.
17
VDDF
-
PWR
Power for 48 Mhz fixed clock buffer.
19
VDDPF
-
PWR
Power for FAST PCI (66 Mhz) clock buffer and PCIF (66
Mhz) clock buffer
22
VDDP
-
PWR
Power for PCI (33 Mhz) clock buffer and PCIF (66 Mhz)
clock buffer
24
CPU
VDDC
O
CPU clock output. See table on page 1 for frequencies.
13
SSON
VDD
I
PU
Spread Spectrum clock modulation pin. Enables Spread
Spectrum EMI reduction when at a logic low (0) level. Has
an internal pull-up resistor.
16
48M
VDDF
O
This pin is a fixed frequency 48 Mhz clock output.
14
OE
VDD
I
Output enable. When at logic level low causes all clock
outputs to be in a Tri-state mode. Has internal pull-up
resistor.
27
REF
VDD
O
This pin is a Buffered output copy of the crystal reference
frequency.
6, 7, 8
FS[0:2]
VDD
PU
I
Frequency selection input pins. See table on page 1 for
functionality. Contain internal pull-up resistors.
4, 10, 12, 15, 20,
23, 26
VSS
-
PWR
Ground pins for the chip.
5, 9, 28
VDD
-
PWR
Power supply pins for analog circuit and core logic.
25
VDDC
-
PWR
Power supply for CPU clock output buffer.
1
VDDR
-
PWR
Power supply for reference clock output buffer.
A bypass capacitor (0.1
F) should be placed as close as possible to each Vdd pin. If these bypass capacitors
are not close to the pins their high frequency filtering characteristic will be canceled by the lead inductance’s of
the traces.
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