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| 型号： | SG5842JADZ |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 10/15页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR FLYBK ISO PWM 8-DIP |
| 产品变化通告： | Product Discontinuation 03/Dec/2009 |
| 标准包装： | 59 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 68kHz |
| 占空比： | 70% |
| 电源电压： | 10.5 V ~ 20 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 包装： | 管件 |
Functional Description
f PWM =
(KHz)
R I (K Ω )
Startup Current
The typical startup current is only 14μA, which allows a
high-resistance, low-wattage startup resistor to be used to
minimize power loss. A 1.5M ? /0.25W startup resistor and
a 10μF/25V V DD hold-up capacitor are sufficient for an
AC/DC adapter with a universal input range.
Operating Current
The required operating current has been reduced to
4mA. This results in higher efficiency and reduces the
V DD hold-up capacitance requirement.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to continuously decrease the PWM
frequency under light-load conditions. To avoid acoustic
noise problems, the minimum PWM frequency is set
above 22KHz. This green-mode function dramatically
reduces power consumption under light-load and zero-
load conditions. Power supplies using this controller can
meet even the strictest international standby power
regulations.
Oscillator Operation
A resistor connected from the RI pin to the GND pin
generates a constant current source for the controller.
This current is used to determine the center PWM
frequency. Increasing the resistance reduces PWM
frequency. Using a 26K ? resistor, R I , results in a
corresponding 65KHz PWM frequency. The relationship
between R I and the switching frequency is:
1690
(1)
The range of the PWM oscillation frequency is designed
as 47KHz ~ 109KHz.
SG5842JA also integrates a frequency hopping function
internally. The frequency variation ranges from around
62KHz to 68KHz for a center frequency of 65KHz. The
frequency hopping function helps reduce EMI emission
of a power supply with minimum line filters.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate drive.
? 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA ? Rev. 1.4.3
10
Under-Voltage Lockout (UVLO)
The turn-on/turn-off thresholds are fixed internally at
16.5V/10.5V. To enable a SG5842A/JA controller during
startup, the hold-up capacitor must first be charged to
16.5V through the startup resistor.
The hold-up capacitor continues to supply V DD before
energy can be delivered from the auxiliary winding of
the main transformer. V DD must not drop below 10.5V
during this startup process. This UVLO hysteresis
window ensures that the hold-up capacitor can
adequately supply V DD during startup.
Gate Output / Soft Driving
The SG5842A/JA BiCMOS output stage is a fast totem-
pole gate driver. Cross-conduction has been avoided to
minimize heat dissipation, increase efficiency, and
enhance reliability. The output driver is clamped by an
internal 18V Zener diode to protect the power MOSFET
transistors from harmful over-voltage gate signals. A
soft-driving waveform is implemented to minimize EMI.
Slope Compensation
The sensed voltage across the current sense resistor is
used for peak-current-mode control and cycle-by-cycle
current limiting. The built-in slope compensation
function improves power supply stability and prevents
peak-current-mode control from causing sub-harmonic
oscillations. Within every switching cycle, the
SG5842A/JA controller produces a positively sloped,
synchronized ramp signal.
Constant Output Power Limit
When the SENSE voltage across the sense resistor,
R S , reaches the threshold voltage, around 0.85V; the
output GATE drive is turned off after a small delay, t PD .
This delay introduces additional current proportional to
t PD ? V IN / L P . The delay is nearly constant regardless of
the input voltage V IN. Higher input voltage results in a
larger additional current and the output power limit is
higher than under low input line voltage. To compensate
this variation for a wide AC input range, a sawtooth
power-limiter (saw limiter) is designed to solve the
unequal power-limit problem. The saw limiter is
designed as a positive ramp signal (V LIMIT_RAMP ) fed to
the inverting input of the OCP comparator. This results
in a lower current limit at high-line inputs than at low-
line inputs.
V DD Over-Voltage Protection (OVP)
V DD over-voltage protection is built in to prevent
damage due to abnormal conditions. Once the V DD
voltage is over the V DD over-voltage protection voltage
(V DD-OVP ) and lasts for t D-OVP , the PWM pulse is latched
off. The PWM pulses stay latched off until the power
supply is unplugged from the mains outlet.
www.fairchildsemi.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SG5842JASY | 功能描述:开关变换器、稳压器与控制器 HI-INTEGRD GRN-MODE PWM CONTROLLER RoHS:否 制造商:Texas Instruments 输出电压:1.2 V to 10 V 输出电流:300 mA 输出功率: 输入电压:3 V to 17 V 开关频率:1 MHz 工作温度范围: 安装风格:SMD/SMT 封装 / 箱体:WSON-8 封装:Reel |
| SG5842JASZ | 功能描述:IC REG CTRLR FLYBK ISO PWM 8-SOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| SG5842JDSY | 功能描述:电流型 PWM 控制器 HI-INTEGRD GRN-MODE PWM CONTROLLER RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| SG5842JDSZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Fairchild Semiconductor Corporation 功能描述: |
| SG5843SZ | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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