参数资料
型号: SG5842JASZ
厂商: Fairchild Semiconductor
文件页数: 4/15页
文件大小: 0K
描述: IC REG CTRLR FLYBK ISO PWM 8-SOP
产品变化通告: Mold Compound Change 12/Dec/2007
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 68kHz
占空比: 70%
电源电压: 10.5 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 105°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
Pin Configuration
Figure 4. Pin Configuration
Pin Definitions
Pin #
1
2
3
4
5
6
7
8
Name
GND
FB
VIN
RI
RT
SENSE
VDD
GATE
Description
Ground
The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is
determined in response to the signal from this pin and the current-sense signal from Pin 6. If FB
voltage exceeds the threshold, the internal protection circuit disables PWM output after a
predetermined delay time.
For startup, this pin is pulled HIGH to the rectified line input via a resistor. Since the startup
current requirement is very small, a large startup resistance can be used to minimize power loss.
A resistor connected from the RI pin to GND provides a constant current source. This determines
the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26K ?
resistor results in a 65KHz center PWM frequency.
For over-temperature protection. An external NTC thermistor is connected from this pin to the
GND pin. The impedance of the NTC decreases at high temperatures. Once the voltage of the
RT pin drops below a fixed limit, PWM output is latched off.
Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle
current limiting.
Power supply. The internal protection circuit disables PWM output if V DD is over-voltage.
The totem-pole output driver for the power MOSFET, which is internally clamped below 18V.
? 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA ? Rev. 1.4.3
4
www.fairchildsemi.com
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