参数资料
型号: SG6742HLSZ
厂商: Fairchild Semiconductor
文件页数: 9/13页
文件大小: 0K
描述: IC CTRLR PWM GREEN CM OVP 8SOP
标准包装: 1
输出隔离: 隔离
频率范围: 90kHz ~ 110kHz
输入电压: 10.5 V ~ 22 V
输出电压: 18V
功率(瓦特): 400mW
工作温度: -40°C ~ 105°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOP
包装: 标准包装
其它名称: SG6742HLSZDKR
Functional Description
Startup Current
For startup, the HV pin is connected to the line input or
bulk capacitor through an external diode and resistor,
R HV , (1N4007 / 100K ? recommended). Typical startup
current drawn from pin HV is 2.3mA and charges the
hold-up capacitor through the diode and resistor. When
the V DD capacitor level reaches V DD-ON , the startup
current switches off. At this moment, the V DD capacitor
only supplies the SG6742HL/HR to keep the V DD before
the auxiliary winding of the main transformer to provide
the operating current.
Operating Current
Operating current is around 2.7mA. The low operating
current enables better efficiency and reduces the
requirement of V DD hold-up capacitance.
Green-Mode Operation
The proprietary green-mode function provides an off-
time modulation to reduce the switching frequency in
the light-load and no-load conditions. The on time is
limited for better abnormal or brownout protection. V FB ,
which is derived from the voltage feedback loop, is
taken as the reference. Once V FB is lower than the
threshold voltage, switching frequency is continuously
decreased to the minimum green-mode frequency of
around 22KHz.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
SENSE pin. The PWM duty cycle is determined by this
current sense signal and V FB , the feedback voltage.
When the voltage on SENSE pin reaches around
V COMP =(V FB –0.6)/4, a switch cycle is terminated
immediately. V COMP is internally clamped to a variable
voltage around 0.85V for output power limit.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate driver.
Gate Output / Soft Driving
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18V Zener diode to protect power MOSFET transistors
against undesirable gate over voltage. A soft driving
waveform is implemented to minimize EMI.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at startup. The built-in 6ms soft-start
circuit significantly reduces the startup current spike
and output voltage overshoot.
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillation.
SG6742HL/HR inserts a synchronized positive-going
ramp at every switching cycle.
Constant Output Power Limit
When the SENSE voltage, across the sense resistor
R S , reaches the threshold voltage, around 1V, the
output GATE drive is turned off after a small delay, t PD .
This delay introduces an additional current proportional
to t PD ? V IN / L P . Since the delay is nearly constant
regardless of the input voltage V IN , higher input voltage
results in a larger additional current and the output
power limit is higher than under low input line voltage.
To compensate this variation for wide AC input range, a
sawtooth power-limiter is designed to solve the unequal
power-limit problem. The power limiter is designed as a
positive ramp signal fed to the inverting input of the
OCP comparator. This results in a lower current limit at
high-line inputs than at low-line inputs.
V DD Over-Voltage Protection (OVP)
V DD over-voltage protection has been built in to prevent
damage due to abnormal conditions. If the V DD voltage
is over the over-voltage protection voltage (V DD-OVP ) and
lasts for t D-VDDOVP , the PWM pulses are disabled until
the V DD voltage drops below the UVLO, then starts
again. Over-voltage conditions are usually caused by
open feedback loops.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 15.5V and 9.5V. During startup, the hold-up capacitor
must be charged to 15.5V through the startup resistor to
enable the IC. The hold-up capacitor continues to
supply V DD before the energy can be delivered from
auxiliary winding of the main transformer. V DD must not
drop below 9.5V during this startup process. This UVLO
hysteresis window ensures that hold-up capacitor is
adequate to supply V DD during startup.
? 2008 Fairchild Semiconductor Corporation
SG6742HL/HR ? Rev. 1.0.4
9
www.fairchildsemi.com
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相关代理商/技术参数
参数描述
SG6742HR 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Highly Integrated Green-Mode PWM Controller
SG6742HR_HL 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Highly Integrated Green-Mode PWM Controller
SG6742HRSY 功能描述:电流型 PWM 控制器 Current Mode PWM Controller 18V RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14
SG6742HRSZ 功能描述:电流型 PWM 控制器 BiCMOS Green-Mode PWM Controll RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14
SG6742ML 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Highly Integrated Green-Mode PWM Controller