参数资料
型号: SG6841DZ
厂商: Fairchild Semiconductor
文件页数: 9/14页
文件大小: 0K
描述: IC REG CTRLR FLYBACK PWM 8-DIP
标准包装: 59
PWM 型: 控制器
输出数: 1
频率 - 最大: 70kHz
占空比: 90%
电源电压: 10 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -20°C ~ 85°C
封装/外壳: 8-DIP(0.300",7.62mm)
包装: 管件
Product Specification
High-integrated Green-mode PWM Controller
OPERATION DESCRIPTION
Start-up current
Typical start-up current is only 30uA so that a high
resistance, and low-wattage, start-up resistor can be used
to minimize power loss. For an AC/DC adapter with
universal input range, a 1.5 M ? , 0.25W, start-up resistor
and a 10uF/25V VDD hold-up capacitor are enough for
this application.
Operating current
Operating current has been reduced to 3mA. The low
operating current enables a better efficiency and reduces
the requirement of VDD hold-up capacitance.
Green Mode Operation
The patented green-mode function provides an
off-time modulation to reduce the switching frequency in
the light load and no load conditions. The on time is
limited for better abnormal or brownout protection. V FB ,
which is derived from the voltage feedback loop, is taken
as the reference. Once V FB is lower than the threshold
voltage, switching frequency will be linearly decreased to
the minimum green mode frequency around 10kHz (R i
=26k ? ).
Oscillator Operation
A resistor from RI pin to ground will generate a
constant current source for SG6841. This current is used
to charge an internal capacitor and hence the internal
clock and switching frequency are determined. Increase
the resistance will decrease the current source and reduce
the switching frequency. A 26k ? resistor R i creates a
50uA constant current I i and generates 65kHz switching
frequency. The relation between Ri and switching
freauency is:
SG6841
Current sensing and PWM current
limiting
Peak current mode control is utilized in SG6841 to
regulate output voltage and provide pulse by pulse current
limiting. The switch current is detected by a sense resistor
into the sense pin of SG6841. The PWM duty cycle is
determined by this current sense signal and V FB , the
feedback voltage. When the voltage on sense pin reaches
V COMP = (V FB –1.0)/3, a switch cycle will be terminated
immediately. V COMP is internally clamped to a variable
voltage around 0.85v for output power limit.
Leading Edge Blanking
Each time when the power MOSFET is switched on,
a turn-on spike will inevitably occur on the sense-resistor.
To avoid premature termination of the switching pulse, a
270 nsec leading-edge blanking time is built in.
Conventional RC filtering can therefore be omitted.
During this blanking period, the current-limit comparator
is disabled and it cannot switch off the gate driver.
Under-voltage lockout (UVLO)
The turn-on and turn-off threshold of SG6841 are
fixed internally at 16V/10V. During start-up, the hold-up
capacitor must be charged to 16V through the start-up
resistor so that SG6841 will be enabled. The hold-up
capacitor will continue to supply V DD before the energy
can be delivered from auxiliary winding of the main
transformer. V DD must not drop below 10V during this
start-up process. This UVLO hysteresis window insures
that hold-up capacitor is adequate to supply V DD during
start-up.
Gate Output / Soft Driving
The SG6841 BiCMOS output stage is a fast totem
pole gate driver. Cross conduction has been avoided to
f PWM =
1690
R I (k Ω )
( kHz ) ---------------------------- (1)
minimize heat dissipation, increases efficiency and
enhances reliability. The output driver is clamped by an
internal 18V Zener diode in order to protect power
The range of the PWM oscillation frequency is
designed as 50kHz ~ 90kHz.
MOSFET transistors against undesirable gate over
voltage. A soft driving waveform is implemented to
minimize EMI.
?System General Corp.
Version 2.1 (IRO33.0001.B5)
-9-
www.sg.com.tw
Jun.15,2006
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