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参数资料
| 型号： | SH3001IMLTRT |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, QCC16 |
| 封装： | 3 X 3 MM, 0.90 MM HEIGHT, LEAD FREE, MLP-16 |
| 文件页数： | 16/20页 |
| 文件大小： | 788K |
| 代理商： | SH3001IMLTRT |
SH3001 MicroBuddy
SYSTEM MANAGEMENT
Copyright 2002-2005 Semtech Corporation
5
V1.15
www.semtech.com
Clock Management System
The SH3001 provides a flexible tool for creating and
managing clocks, a versatile and accurate “any
frequency” clock synthesizer (see Figure 1).
It is capable of generating any frequency in the
range of 62.5 kHz to 16.0 MHz, with worst-case
resolution of 0.0256% (256 ppm). The internal
32.768 kHz clock can also be routed to the CLKOUT pin
(and HF oscillator stopped for energy savings).
The objectives, features, and behavior of the Clock
Management System are aimed towards the systems
that utilize a microcontroller, a microprocessor, a DSP or
an ASIC.
The SH3001 permits the automatic sensing of the
intentions of the host processor, an industry first. The
SH3001 shuts down its clock output when it senses that
the host processor issued a STOP instruction.
Subsequently, the SH3001 idles, consuming less than
10 A. As soon as the host exits the STOP mode, the
SH3001 instantaneously starts to supply a stable clock
(<2s wake-up).
A typical system, constructed with a ceramic
resonator or a crystal as the frequency determining
element, must wait at least several hundred
microseconds (for a resonator), or as much as 100 ms or
more (for a HF crystal), to re-start the oscillator. The
SH3001 allows the response to and service of an event
to finish with a speed previously unattainable for a
simple microprocessor. A system with a traditional clock
approach can be as much as 100x – 10,000x slower.
Clock Generator Operation
The frequency synthesizer in the SH3001 is
constructed from the 2:1 tunable 8.0 –16.0 MHz HF
oscillator followed by a programmable “power-of-two”
post-divider (see Figure 1).
The Clock Source selector and the programmable
post-scale divider allow instantaneous switching
between the 32.768 kHz internal clock and divided-down
HF oscillator output. There is no settling or instability
when the switch occurs.
This is a preferred method for clock control in
computing systems, when the large ratio between high
and low frequency of operations allows for
correspondingly large and instantaneous savings in
power consumption.
Post-scaler
(Divide by 1, 2, 4,
8, 16, 32, 64, 128)
Figure 1. Simplified HF Oscillator System
32.768 kHz
START/STOP
16
15
CLKOUT
CLKIN
Clock Buffer
and Glue
Logic
HF Digitally
Controlled
Oscillator
8-16 MHz
18-bit
DCO Code
Register
Clock On
Force
DCO On
Clock Source
1
0
Spectrum
Spreading
Controls
Frequency Locked Loop
Logic
13-bit
Frequency
Set value
÷ 16 2048 Hz
8-bit Pseudo-
Random Noise
Generator
FLL On
From / To
Serial I/O
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PDF描述 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SH3002 | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:Reset Management and Clock Management Support IC for Microcontrollers |
| SH3002-DC70A | 制造商:ROHM 制造商全称:Rohm 功能描述:Near edge thermal printhead (with thermal historical control) |
| SH3002-DC80A | 制造商:ROHM 制造商全称:Rohm 功能描述:Near edge thermal printhead (with thermal historical control) |
| SH3002-DC90A | 制造商:ROHM 制造商全称:Rohm 功能描述:Near edge type thermal printhead(11.81dots / mm) |
| SH3002-DC90A_09 | 制造商:ROHM 制造商全称:Rohm 功能描述:Near edge type thermal printhead(11.81dots / mm) |
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