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| 型号： | SI3063-F-FS |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 15/62页 |
| 文件大小： | 0K |
| 描述： | IC DAA ENH GLOB LINE-SIDE 16SOIC |
| 标准包装： | 48 |
| 功能： | 直接存取装置（DAA） |
| 电路数： | 1 |
| 电流 - 电源： | 9mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC N |
| 包装： | 管件 |
| 包括： | 结帐音调检测，线路电压监视器，回路电流监视器，过载检测，振铃检测器 |
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Si306x
22
Rev. 0.9
designed to satisfy minimum return loss requirements
for every country in the world that requires a complex
termination. For any of the ac termination settings, the
programmable digital hybrid can be used to further
reduce near-end echo. See the following “6.16.
Transhybrid Balance” section for more details.
6.16. Transhybrid Balance
The DAA contains an on-chip analog hybrid that
performs the 2- to 4-wire conversion and near-end echo
cancellation. This hybrid circuit is adjusted for each ac
termination setting selected.
6.17. Ring Detection
The ring signal is resistively coupled from TIP and RING
to the RNG1 and RNG2 pins. The DAA supports either
full- or half-wave ring detection. With full-wave ring
detection, the designer can detect a polarity reversal of
the ring signal. See “6.24. Caller ID” on page 25. The
ring detection threshold is programmable with the RT bit
(Register 16, bit 0).
The ring detector mode is controlled by the RFWE bit
(Register 18). When the RFWE bit is 0 (default mode),
the ring detector operates in half-wave rectifier mode. In
this mode, only positive ring signals are detected. A
positive ring signal is defined as a voltage greater than
the ring threshold across RNG1-RNG2. Conversely, a
negative ring signal is defined as a voltage less than the
negative ring threshold across RNG1-RNG2. When the
RFWE bit is 1, the ring detector operates in full-wave
rectifier mode. In this mode, both positive and negative
ring signals are detected.
The ring detector output can be monitored in one of two
ways. The first method uses the register bits RDTP,
RDTN, and RDT (Register 5). The second method uses
the SDO output internal to the integrated system-side
module.
The ring detector mode is controlled by the RFWE bit
(Register 18). When the RFWE bit is 0 (default mode),
the ring detector operates in half-wave rectifier mode. In
this mode, only positive ring signals are detected. A
positive ring signal is defined as a voltage greater than
the ring threshold across RNG1-RNG2. Conversely, a
negative ring signal is defined as a voltage less than the
negative ring threshold across RNG1-RNG2. When the
RFWE bit is 1, the ring detector operates in full-wave
rectifier mode. In this mode, both positive and negative
ring signals are detected.
The first ring detect method uses the ring detect bits
(RDTP, RDTN, and RDT). The RDTP and RDTN
behavior is based on the RNG1-RNG2 voltage. When
the signal on RNG1-RNG2 is above the positive ring
threshold the RDTP bit is set. When the signal on
RNG1-RNG2 is below the negative ring threshold the
RDTN bit is set. When the signal on RNG1-RNG2 is
between these thresholds, neither bit is set.
The RDT behavior is also based on the RNG1-RNG2
voltage. When the RFWE bit is 0, a positive ring signal
sets the RFWE bit for a period of time. When the RFWE
bit is 1, a positive or negative ring signal sets the RDT
bit.
The RDT bit acts like a one shot. When a new ring
signal is detected, the one shot is reset. If no new ring
signals are detected prior to the one shot counter
reaching 0, then the RDT bit clears. The length of this
count is approximately 5 seconds. The RDT bit is reset
to 0 by an off-hook event. If the RDTM bit
(Register 3, bit 7) is set, a hardware interrupt occurs on
the INT port when RDT is triggered. This interrupt can
be cleared by writing to the RDTI bit (Register 4, bit 7).
When the RDI bit (Register 2, bit 2) is set, an interrupt
occurs on both the beginning and end of the ring pulse
as defined by the RTO bits (Register 23, bits 6:3). Ring
validation may be enabled when using the RDI bit.
The second ring detect method uses the serial
communication interface to transmit ring data. If the
communications link is active (PDL=0) and the device is
not off-hook or not in on-hook line monitor mode, the
ring data is presented on SDO. The waveform on SDO
depends on the state of the RFWE bit.
When the RFWE bit is 0, SDO is –32768 (8000h) when
the RNG1-RNG2 voltage is between the thresholds. On
ring detection, SDO transitions to +32767 when the ring
signal is positive, then goes back to –32768 when the
ring is near 0 and negative. Therefore, a near square
wave is presented on SDO that swings from –32768 to
+32767 in cadence with the ring signal.
When the RFWE bit is 1, SDO sits at approximately
+1228 when the RNG1-RNG2 voltage is between the
thresholds. When the ring becomes positive, SDO
transitions to +32767. When the ring signal is near 0,
SDO remains near 1228. As the ring signal becomes
negative, the SDO transitions to –32768. This repeats in
cadence with the ring signal.
To observe the ring signal on SDO, observe the MSB of
the data. The MSB toggles at the same frequency as
the ring signal independent of the ring detector mode.
This method is adequate for determining the ring
frequency.
6.18. Ring Validation
This feature prevents false triggering of a ring detection
by validating the ring parameters. Invalid signals, such
as a line voltage change when a parallel handset goes
off-hook, pulse dialing, or a high-voltage line test are
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相关代理商/技术参数 |
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|---|---|
| SI3063-F-FSR | 制造商:Silicon Laboratories Inc 功能描述:INTEGRATED DIRECT ACCESS ARRANGEMENT 16SOIC - Tape and Reel |
| SI3063-X-FS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:GLOBAL LINE-SIDE DAA FOR EMBEDDED SYSTEM-SIDE MODULE |
| SI3064 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:GLOBAL LINE-SIDE DAA FOR EMBEDDED SYSTEM-SIDE MODULE |
| SI3065 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:GLOBAL LINE-SIDE DAA FOR EMBEDDED SYSTEM-SIDE MODULE |
| SI3065-X-FS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:GLOBAL LINE-SIDE DAA FOR EMBEDDED SYSTEM-SIDE MODULE |
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