参数资料
型号: SI3232PPTX-EVB
厂商: Silicon Laboratories Inc
文件页数: 105/128页
文件大小: 0K
描述: BOARD EVAL W/DISCRETE INTERFACE
标准包装: 1
系列: ProSLIC®
主要目的: 接口,模拟前端(AFE)
已用 IC / 零件: Si3232
已供物品: 板,CD
Si3232
78
Preliminary Rev. 0.96
Not
Recommended
fo
r N
ew
D
esi
gn
s
Reset settings = 0x00
MSTRSTAT: Master Initialization Status (Register Address 3)
(Register type: Initialization/single value instance for both channels)
Bit
D7
D6D5D4D3
D2
D1
D0
Name
PLLFAULT FSFAULT PCFAULT
SRCLR
PLOCK
FSDET
FSVAL
PCVAL
Type
R/W
R
RRRR
Bit
Name
Function
7
PLLFAULT
PLL Lock Fault Status.
This bit is set when the PLOCK bit transitions low, indicating loss of PLL lock. Writing 1 to
this bit clears the status.
0 = PLL lock is valid.
1 = PLL has lost lock.
6FSFAULT
FSYNC Clock Fault Status.
This bit is set when the FSVAL and FSDET bits transition low, indicating loss of valid
FSYNC signal or invalid FSYNC-to-PCLK ratio. Writing 1 to this bit clears the status.
0 = Correct FSYNC to PCLK ration present.
1 = FSYNC to PCLK ratio lost.
5PCFAULT
PCM Clock Fault Status.
This bit will be set when the PCVAL bit transitions low. Writing 1 to this bit clears the status.
0 = Valid PCLK signal present.
1 = No valid PCLK signal present.
4SRCLR
SRAM Clear Status Detect.
0 = SRAM clear operation not initiated or in progress.
1 = SRAM clear operation has completed.
3PLOCK
PLL Lock Detect.
Indicates the internal PLL is locked relative to FSYNC.
0 = PLL has lost lock relative to FSYNC.
1 = PLL locked relative to FSYNC.
2
FSDET
FSYNC to PCLK Ratio Detect.
Indicates a valid FSYNC to PCLK ratio has been detected.
0 = Invalid FSYNC to PCLK ratio detected.
1 = Correct FSYNC to PCLK ratio present.
1FSVAL
FSYNC Clock Valid.
Indicates that a minimum valid FSYNC signal is present.
0 = FSYNC signal is not valid.
1 = FSYNC signal is present.
0PCVAL
PCM Clock Valid.
Indicates that a minimum valid PCLK signal is present.
0 = PCLK signal is
128 kHz.
1 = PCLK signal is
128 kHz.
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