参数资料
型号: SI3460-E02-GM
厂商: Silicon Laboratories Inc
文件页数: 9/24页
文件大小: 0K
描述: IC POWER MANAGEMENT CTLR 11VQFN
标准包装: 122
应用: 供电设备(PSE)
电流 - 电源: 500mA
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-VFDFN 裸露焊盘
供应商设备封装: 11-QFN(3x3)
包装: 管件
Si3460
3.1. PSE Timing Characteristics
When implemented in accordance with the recommended external components and layout guidelines, the Si3460
controller enables the following typical performance characteristics in single-port PSE applications. Refer to the
Si3460-EVB applications note, schematics, and user's guide for more details.
Table 6. PSE Timing*
Description
Endpoint detection delay
cycle
Detection time
Classification delay cycle
Classification time
Symbol
t DET_CYCLE
t DETECT
t CLASS_CYCLE
t CLASS
Test Conditions
Time from PD connection to port to
completion of detection process.
Time required to measure PD
signature resistance.
Time from successful detect mode
to classification complete.
Min
70
10
10
Typ
70
Max
400
50
50
Unit
ms
ms
ms
ms
Power-up turn-on delay
Time from when a valid detection is
t PWRUP
completed until V OUT power is
30
ms
applied
Midspan detect backoff time
Current limit time
Disconnect delay
t BOM
t LIM
t DC_DIS
2
60
350
s
ms
ms
*Note: These typical specifications are based on an ambient operating temperature of 25 oC and V IN = +12 V.
3.1.1. PSE Timing Diagrams
The basic sequence of applying power is shown in Figure 2. Following is the description of the function that must
be performed in each phase.
57 V
44 V
20.5 V
15.5 V
10 V
2.8 V
t DET_CYCLE
t CLASS_CYCLE
Time
(msec)
t PWRUP
Figure 2. Detection, Classification, Powerup, and Disconnect Sequence
Rev. 1.2
9
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