参数资料
型号: SI3480MS8-KIT
厂商: Silicon Laboratories Inc
文件页数: 11/14页
文件大小: 0K
描述: KIT EVAL 8PORT SI3480/52/SI3500
标准包装: 1
主要目的: 电源管理,以太网供电(POE),PSE
嵌入式:
已用 IC / 零件: Si3452,Si3480,Si3500
已供物品: 板,线缆,CD
相关产品: SI3480-A01-GM-ND - IC CTLR 4/8-PORT POE 20-QFN
336-1830-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1829-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1831-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1834-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1844-5-ND - IC POE SWITCH PWR OVER LAN 20QFN
336-1833-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
336-1832-5-ND - IC POE CONTROLLER MIDSPAN 40QFN
Si3480
8. Landing Pattern: 20-Pin QFN
Figure 3 illustrates the landing pattern for the Si3480. Table 8 lists the values for the dimensions shown in the
illustration.
Figure 3. QFN-20 Recommended PCB Land Pattern
Table 8. QFN-20 PCB Land Pattern Dimensions
Dimension
C1
C2
E
Min
3.70
3.70
0.50
Max
Dimension
X2
Y1
Y2
Min
2.15
0.90
2.15
Max
2.25
1.00
2.25
X1
0.20
0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 ? m minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
8. A 2x2 array of 0.95mm openings on a 1.1 mm pitch should be used for the center pad to
assure the proper paste volume (71% Paste Coverage).
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Rev. 1.0
11
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