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参数资料
| 型号： | SI4022-A0-FT |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 11/20页 |
| 文件大小： | 726K |
| 描述： | IC TX FSK UNI 868/915MHZ 16TSSOP |
| 标准包装： | 96 |
| 频率： | 868MHz，915MHz |
| 应用： | ISM |
| 调制或协议： | FSK |
| 数据传输率 - 最大： | 115.2kbps |
| 功率 - 输出： | 6dBm |
| 电流 - 传输： | 24mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 电源电压： | 2.2 V ~ 3.8 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 管件 |
11
Si4022
bit 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
POR
1
1
0
0
0
0
0
0
0
0
ex es etr eb
et
dc
C002h
bit 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
POR
1
0
1
0
f11 f10 f9
f8
f7
f6
f5
f4
f3
f2
f1
f0
AD57h
Band [MHz]
C
868
10
915
11
Power Management Command
Bit 5 <ex>:
Enables the the crystal oscillator.
Bit 4 <es>:
Enables the synthesizer.
Bit 3 <etr>:
Enables the power amplifier. If the ex and es bit is not set, it switches on the crystal oscillator and the
synthesizer as well.
In FIFO mode (bit fe is set in the FIFO Setting Command) setting this bit will roll out the content of the FIFO.
Bit 2 <eb>:
Enables the low battery detector.
Bit 1 <et>:
Enables the wake-up timer.
Bit 0 <dc>:
Disables the clock output buffer.
The constant C is determined by
the selected band as:
Frequency Setting Command
The 12-bit parameter of the Frequency Setting
Command has the value F. The value F
should be in the range of 96 and 3903. When F is out
of range, the previous value is kept. The synthesizer
center frequency f
0
can be calculated as:
f
0
= 8 * 10 MHz * (C + F/4000)
Bit
7
6
5
4
3
2
1
0
POR
1
1
0
0
0
1
1
0
-
Transmitter FIFO Write Command
With this command, the controller can write databits to the transmitter FIFO. Bit (fe) must be set in the FIFO Setting Command.
Note
Note
Note
Note
Note: If faster operation is needed, then leave ex and es bit set to 1 and toggle only the etr bit.
Power Saving Modes
The different operating modes of the chip depend on the following control bits:
Operating Mode
eb or et
es
etr
ex
Active (transmit)
X
x
1
x
Idle
X
0
0
1
Sleep
1
0
0
0
Standby
0
0
0
0
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