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参数资料
| 型号： | SI4022-A1-FT |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 18/20页 |
| 文件大小： | 726K |
| 描述： | IC TX FSK 915MHZ 3.8V 16-TSSOP |
| 标准包装： | 96 |
| 频率： | 868MHz，915MHz |
| 应用： | ISM |
| 调制或协议： | FSK |
| 数据传输率 - 最大： | 115.2kbps |
| 功率 - 输出： | 6dBm |
| 电流 - 传输： | 24mA |
| 数据接口： | PCB，表面贴装 |
| 天线连接器： | PCB，表面贴装 |
| 电源电压： | 2.2 V ~ 3.8 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 管件 |
| 其它名称： | 336-1623-5 |
18
Si4022
EXAMPLE APPLICATIONS: DATA PACKET TRANSMISSION
Data packet structure
Data packet structure
Data packet structure
Data packet structure
Data packet structure
An example data packet structure using theSi4022 Si4022 pair for data transmission. This packet structure is an example of how to use the
high efficiency FIFO mode at the receiver side:
AA
AA
AA
2D
D4
Databytes (received in the
FIFO of the receiver)
Preamble
Synchron pattern
D
0
D
1
D
2
. . .
D
N
The first 3 bytes compose a 24 bit length 01 pattern to let enough time for the clock recovery of the receiver to lock. The next two bytes
compose a 16 bit synchron pattern which is essential for the receivers FIFO to find the byte synchron in the received bit stream. The
synchron patters is followed by the payload. The first byte transmitted after the synchron pattern (D
0
in the picture above) will be the first
received byte in the FIFO.
Important:
Important:
Important:
Important:
Important: The bytes of the data stream should follow each other continuously, otherwise the clock recovery circuit of the receiver side
will be unable to track.
Further details of packet structures can be found in the IA ISM-UGSB1 software development kit manual.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI-40232 | 制造商:BEL 制造商全称:Bel Fuse Inc. 功能描述:SI-40232 |
| SI-40233 | 制造商:BEL 制造商全称:Bel Fuse Inc. 功能描述:SI-40233 |
| SI-40234 | 制造商:BEL 制造商全称:Bel Fuse Inc. 功能描述:SI-40234 |
| SI-40235 | 制造商:BEL 制造商全称:Bel Fuse Inc. 功能描述:SI-40235 |
| SI-40236 | 制造商:BEL 制造商全称:Bel Fuse Inc. 功能描述:SI-40236 |
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