参数资料
型号: SI4112-D-GMR
厂商: Silicon Laboratories Inc
文件页数: 36/36页
文件大小: 0K
描述: IC SYNTHESIZER IF ONLY 28MLP
标准包装: 2,500
类型: 频率合成器
PLL:
输入: 时钟
输出: 时钟
电路数: 1
比率 - 输入:输出: 1:2
差分 - 输入:输出: 无/无
频率 - 最大: 1GHz
除法器/乘法器: 是/无
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-VFQFN 裸露焊盘
供应商设备封装: 28-QFN(5x5)
包装: 带卷 (TR)
Si4133
Rev. 1.61
9
RF1 Harmonic Suppression
Second Harmonic
–26
–20
dBc
RF2 Harmonic Suppression
–26
–20
dBc
IF Harmonic Suppression
–26
–20
dBc
RFOUT Power Level
ZL = 50
–8
–3
1
dBm
RFOUT Power Level2
Z
L = 50RF1 active,
Extended frequency
operation
–14
–7
1
dBm
IFOUT Power Level
ZL = 50
–8
–4
0
dBm
RF1 Output Reference Spurs
Offset = 200 kHz
–65
dBc
Offset = 400 kHz
–71
dBc
Offset = 600 kHz
–75
dBc
RF2 Output Reference Spurs
Offset = 200 kHz
–65
dBc
Offset = 400 kHz
–71
dBc
Offset = 600 kHz
–75
dBc
Powerup Request to Synthesizer Ready3
Time
tpup
Figures 4, 5
40/f
50/f
Powerdown Request to Synthesizer Off4
Time
tpdn
Figures 4, 5
100
ns
Table 5. RF and IF Synthesizer Characteristics (Continued)
(VDD = 2.7 to 3.6 V, TA = –40 to 85 °C)
Parameter1
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. f = 200 kHz, RF1 = 1.6 GHz, RF2 = 1.2 GHz, IFOUT = 550 MHz, LPWR = 0, for all parameters unless otherwise noted.
2. Extended frequency operation only. VDD 3.0 V, QFN only, VCO Tuning Range fixed by directly shorting the RFLA and
RFLB pins. See Application Note 41 for more details on the Si4133 extended frequency operation.
3. From powerup request (PWDN
or SEN during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF
synthesizers ready (settled to within 0.1 ppm frequency error).
4. From powerdown request (PWDN
, or SENduring a write of 0 to bits PDIB and PDRB in Register 2) to supply current
equal to IPWDN.
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