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| 型号： | SI5310-EVB |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 4/26页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR SI5310 |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟发生器 |
| 已用 IC / 零件： | SI5310 |
| 已供物品： | 板 |
| 其它名称： | 336-1140 |
Si5310
12
Rev. 1.3
4. Functional Description
The Si5310 is an integrated clock multiplier and clock
regenerator device based on SIlicon Laboratories
DSPLL technology. The DSPLL phase locks to the
clock input signal (CLKIN) and generates a phase-
locked output clock (MULTOUT) at a multiple of the
input clock frequency. The DSPLL is also employed to
regenerate an output clock (CLKOUT) that is a jitter-
attenuated version of the input clock with clean rising
and falling edges.
The MULTOUT output is configured to operate in either
the 150–167 MHz or the 600–668 MHz frequency range
using the MULTSEL control input. A reference clock
input signal (REFCLK) is used by the DSPLL as a
reference for determination of the PLL lock status. For
convenience, REFCLK can be provided at any one of
five frequencies, each a multiple of the CLKIN
frequency. The REFCLK rate is automatically detected,
so no control inputs are needed for configuration. The
REFCLK input can be synchronous or asynchronous
with respect to the CLKIN input. The operating ranges
for the CLKIN, CLKOUT, MULTOUT, and REFCLK
signals are indicated in Table 9. Typical values for
several applications are presented in Table 10.
Table 9. CLKIN, CLKOUT, MULTOUT, REFCLK Operating Ranges
MULTSEL
CLKIN Range
(MHz)
REFCLK = 2n x CLKIN
±100 ppm
(See Note 1)
CLKOUT
MULTOUT
0
(MULTOUT = 600–668 MHz)
37.500–41.750
n = –2, –1, 0, 1, 2
1xCLKIN
16xCLKIN
75.000–83.500
n = –3, –2, –1, 0, 1
1xCLKIN
8xCLKIN
150.000–167.000
n = –4, –3, –2, –1, 0
1xCLKIN
4xCLKIN
300.000–334.000
n = –5, –4, –3, –2, –1
1xCLKIN
2xCLKIN
600.000–668.000
n = –6, –5, –4, –3, –2
See Note 2
1xCLKIN
1
(MULTOUT = 150–167 MHz)
9.375–10.438
n = 0, 1, 2, 3, 4
1xCLKIN
16xCLKIN
18.750–20.875
n = –1, 0, 1, 2, 3
1xCLKIN
8xCLKIN
37.500–41.750
n = –2, –1, 0, 1, 2
1xCLKIN
4xCLKIN
75.000–83.500
n = –3, –2, –1, 0, 1
1xCLKIN
2xCLKIN
150.000–167.000
n = –4, –3, –2, –1, 0
See Note 2
1xCLKIN
Note:
1. The REFCLK input can be set to any one of the five CLKIN multiples indicated. The REFCLK input can be
asynchronous to the CLKIN input, but must be within ±100 ppm of the stated CLKIN multiple.
2. The CLKOUT output is not valid for MULTOUT:CLKIN ratios of 1:1 (MULTOUT = 1 x CLKIN.)
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