参数资料
型号: SI5334C-A00099-GM
厂商: SILICON LABORATORIES
元件分类: 时钟及定时
英文描述: PLL BASED CLOCK DRIVER, QCC24
封装: 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24
文件页数: 9/34页
文件大小: 233K
代理商: SI5334C-A00099-GM
Si5334
Preliminary Rev. 0.16
17
2.10. Spread Spectrum
Figure 3. Spread Spectrum Triangle Waveform
To reduce the electromagnetic interference (EMI), the
Si5334K/L/M supports PCI Express compliant spread
spectrum on all outputs that are 100 MHz. If CLK0 has
spread spectrum enabled, then the Finc/Fdec function
is not available on CLK0. Spread spectrum modulation
spreads the energy across many frequencies to reduce
the EMI across a narrow range of frequencies.
The modulation rate is the time required to transition
from the maximum spread spectrum frequency to the
minimum spread spectrum frequency and then back to
the maximum frequency as shown in Figure 3.
The Si5334K/L/M supports 0.5% downspread at a 30–
33 kHz rate with a clock frequency of 100 MHz in
compliance with the PCI Express standard. When pin
12 (SSPB) is low the factory-programmed clock outputs
will have spread spectrum turned on.
2.11. Device Reset
To reset the device, a power cycle must be performed.
2.12. LOSLOL Pin
When either a Loss of LOck (LOL) or Loss of Signal
(LOS) condition occurs the LOSLOL pin will assert.
The LOS condition occurs when there is no input clock
input to the Si5334. The loss of lock algorithm works by
continuously
monitoring
the
frequency
difference
between the two inputs of the phase frequency detector.
When
this
frequency
difference
is
greater
than
1000 ppm, a loss of lock condition is declared. Note that
the VCO will track the input clock frequency for up to
~50000 ppm, which will keep the inputs to the phase
frequency detector at the same frequency until the PLL
comes out of lock. When a clock input is removed, the
LOSLOL pin will assert, and the clock outputs may drift
up to 5%. When the input clock with an appropriate
frequency is re-applied, the PLL will again lock.
2.13. Power-Up
Upon powerup, the device performs an internal self-
calibration before operation to optimize loop parameters
and jitter performance. While the self-calibration is
being performed, the device VCO is being internally
controlled by the self-calibration state machine and the
LOL alarm is masked. The output clocks appear after
the device finishes self calibration.
2.14. Factory Programming Options
Silicon Labs Si5334 clock generators are factory-
programmable devices. The functions and frequency
plans can be customized to meet the needs of your
applications. Contact your local Silicon Labs sales
representative.
Ou
tput
C
lock
Fr
equ
ency
Modulation Rate
Time
相关PDF资料
PDF描述
SI5334C-A00141-GM PLL BASED CLOCK DRIVER, QCC24
SI5334M-A00167-GMR PLL BASED CLOCK DRIVER, QCC24
SI5334A-A00102-GMR PLL BASED CLOCK DRIVER, QCC24
SI5334C-A00101-GMR PLL BASED CLOCK DRIVER, QCC24
SI5334C-A00132-GMR PLL BASED CLOCK DRIVER, QCC24
相关代理商/技术参数
参数描述
SI5334C-A00103-GM 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Rail/Tube
SI5334C-A00103-GMR 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel
SI5334C-A00104-GM 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Rail/Tube
SI5334C-A00104-GMR 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel
SI5334C-A00112-GM 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Rail/Tube