参数资料
型号: SI5334C-A00135-GMR
厂商: SILICON LABORATORIES
元件分类: 时钟及定时
英文描述: PLL BASED CLOCK DRIVER, QCC24
封装: 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24
文件页数: 32/34页
文件大小: 233K
代理商: SI5334C-A00135-GMR
Si5334
Preliminary Rev. 0.16
7
Table 6. Input and Output Clock Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Input Clock (AC Coupled Differential Input Clocks on Pins IN1/2, IN5/6)
Frequency
fIN
5
710
MHz
Differential Voltage
Swing
VPP
710 MHz input
0.4
2.4
VPP
Rise/Fall Time
tR/tF
20%–80%
1.0
ns
Duty Cycle1
DC
< 1 ns tr/tf
40
60
%
Input Impedance
RIN
10
k
Input Capacitance
CIN
—3.5
pF
Input Clock (DC-Coupled Single-Ended Input Clock on Pins IN3/4)
Frequency
fIN
CMOS
5
200
MHz
Input Voltage
VI
–0.1
3.63
Vpp
Input Voltage Swing
200 MHz
0.8
3.73
V
Rise/Fall Time
tR/tF
20%–80%
2
ns
Duty Cycle2
DC
< 2 ns tr/tf
40
60
%
Input Capacitance
CIN
—2.0
pF
Output Clocks (Differential)
Frequency3
fOUT
LVPECL, LVDS
0.16
350
MHz
367
466
MHz
550
710
MHz
HCSL
0.16
250
MHz
LVPECL Output
Voltage
VOC
common mode
VDDO
1.4 V
—V
VSEPP
peak-to-peak single-
ended swing
0.55
0.8
0.96
VPP
LVDS Output Voltage
(2.5/3.3 V)
VOC
common mode
1.125
1.2
1.275
V
VSEPP
peak-to-peak single-
ended swing
0.25
0.35
0.45
VPP
LVDS Output
Voltage (1.8 V)
VOC
common mode
0.8
0.875
0.95
V
VSEPP
peak-to-peak single-
ended swing
0.25
0.35
0.45
VPP
Notes:
1. For best jitter performance, keep the input slew rate on IN1/2, IN5/6 faster than 0.3 V/ns.
2. For best jitter performance, keep the input single ended slew rate on pins 3 or 4 faster than 1 V/ns.
3. Only two unique frequencies above Fvco/8 can be simultaneously output, Fvco/4 and Fvco/6.
4. Includes effect of internal series 22
resistor.
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