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参数资料
| 型号： | SI5338H-AXXXXXGMR |
| 厂商： | SILICON LABORATORIES |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 350 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24 |
| 封装： | 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24 |
| 文件页数： | 10/42页 |
| 文件大小： | 380K |
| 代理商： | SI5338H-AXXXXXGMR |
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Si5338
18
Rev. 1.0
Synthesis of the output clocks is performed in two
stages, as shown in Figure 5. The first stage consists of
a high-frequency analog phase-locked loop (PLL) that
multiplies the input stage to a frequency within the
range of 2.2 to 2.84 GHz. Multiplication of the input
frequency is accomplished using a proprietary and
highly precise MultiSynth feedback divider (N), which
allows the PLL to generate any frequency within its
VCO range with much less jitter than typical fractional N
PLL.
Figure 5. Synthesis Stages
The second stage of synthesis consists of the output
MultiSynth dividers (MSx). Based on a fractional N
divider, the MultiSynth divider shown in Figure 6
switches seamlessly between the two closest integer
divider values to produce the exact output clock
frequency with 0 ppm error.
To eliminate phase error generated by this process, the
MultiSynth block calculates the relative phase difference
between the clock produced by the fractional-N divider
and the desired output clock and dynamically adjusts
the phase to match the ideal clock waveform. This novel
approach makes it possible to generate any output
clock frequency without sacrificing jitter performance.
This architecture allows the output of each MultiSynth to
produce any frequency from 5 to Fvco/8 MHz. To
support higher frequency operation, the MultiSynth
divider can be bypassed. In bypass mode, integer divide
ratios of 4 and 6 are supported. This allows for output
frequencies of Fvco/4 and Fvco/6 MHz, which translates
to 367–473.33 MHz and 550–710 MHz respectively.
Because each MultiSynth uses the same VCO output,
there are output frequency limitations when output
frequencies greater than Fvco/8 are desired.
For example, if 375 MHz is needed at the output of
MultiSynth0, the VCO frequency would need to be
2.25 GHz. Now, all the other MultiSynths can produce
any frequency from 5 MHz up to a maximum frequency
of 2250/8 = 281.25 MHz. MultiSynth1,2,3 could also
produce Fvco/4 = 562.5 MHz or Fvco/6 = 375 MHz. Only
two unique frequencies above Fvco/8 can be output:
Fvco/6 and Fvco/4.
Figure 6. Silicon Labs’ MultiSynth Technology
Phase
Frequency
Detector
Loop
Filter
VCO
MultiSynth
÷MS0
MultiSynth
÷MS1
MultiSynth
÷MS2
MultiSynth
÷MS3
MultiSynth
÷N
Synthesis
Stage 1
(APLL)
Synthesis
Stage 2
ref
fb
From
Input
Stage
T
o
Output
S
tage
2.2-2.84 GHz
Fractional-N
Divider
Phase
Adjust
Phase Error
Calculator
Divider Select
(DIV1, DIV2)
fVCO
fOUT
MultiSynth
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5338H-B00191-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5338H-B00300-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338H-B00300-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5338H-B00385-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338H-B00385-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
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