参数资料
型号: SI8501-C-IS
厂商: Silicon Laboratories Inc
文件页数: 17/36页
文件大小: 0K
描述: SENSOR CURR 5A 5.5V UNI 20SOIC
标准包装: 38
电流 - 感应: 5A
精确度: ±5%
灵敏度: 392mV/A
电流 - 电源: 4mA
传感器类型: 闭环
电源电压: 2.7 V ~ 5.5 V
输出: 可配置
频率: 50kHz ~ 1MHz
电极标记: 单向
工作温度: -40°C ~ 125°C
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
包装: 管件
产品目录页面: 627 (CN2011-ZH PDF)
其它名称: 336-1721-5
Si85xx
As explained in Section “2.3. Integrator Reset and Current Measurement”, the signals applied to R1–R4 can
control integrator reset in real time (Option 1), or they can trigger a reset event of programmable duration (Option
2). Referring to Figure 14, reset timing is exclusively a function of the signals applied to R1–R4 when TRST is tied
to VDD.
If not connected to VDD, the reset timer is enabled, and TRST must be connected through a resistor to ground to
set the reset duration (t R ). Note that the reset timer is retriggerable and generates a timed integrator discharge
pulse whenever the reset logic output transitions from low to high.
MODE = 1
R1
R2
R3
R4
R4 = 0
MODE = 1
R4 = 1
Output 1
Output 2
TRST = VDD
Reset timing determined
only by inputs R1–R4.
RESET
TIMER
PGM
OUT
CLK
1
0
+
TRST = R1 to GND
Reset triggered by inputs
R1–R4. Reset time (t R ) set
by value of resistor R TRST .
TRST
VREF
MODE = 0
Output 3
Logic level gate
SYSTEM
CONTROLLER
control signals
(to Rn inputs)
INTEGRATOR
External
Driver
Internal
Driver
Logic level gate
control signals
Required if driver
(to Rn inputs)
output voltage > VDD
Figure 14. Si851x Integrator Reset Logic
Preliminary Rev. 0.4
17
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