参数资料
| 型号： | SI9104DW-E3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 3/7页 |
| 文件大小： | 0K |
| 描述： | IC REG MULTI CONFIG 4V 16SOIC |
| 标准包装： | 528 |
| 类型： | 回扫，正向转换器，隔离式 |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 4V |
| 输入电压： | 10 V ~ 120 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 40kHz ~ 1MHz |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-SOIC |
Product is End of Life 3/2014
Si9104
Vishay Siliconix
SPECIFICATIONS a
Test Conditions
Unless Otherwise Specified
DISCHARGE = - V IN = 0 V
Limits
D Suffix - 40 to 85 °C
Parameter
Symbol
V CC = 10 V, + V IN = 48 V
R BIAS = 390 k Ω , R OSC = 330 k Ω
Temp b
Min d
Typ c
Max d
Unit
Error Amplifier
Feedback Input Voltage
Input BIAS Current
Input OFFSET Voltage
Open Loop Voltage Gain e
Unity Gain Bandwidth e
Dynamic Output Impedance e
Output Current
Power Supply Rejection
V FB
I FB
V OS
A VOL
BW
Z OUT
I OUT
PSRR
FB Tied to COMP
OSC IN = - V IN (OSC Disabled)
OSC IN = - V IN , V FB = 4 V
OSC IN = - V IN (OSC Disabled)
Source (V FB = 3.4 V)
Sink (V FB = 4.5 V)
10 V ≤ V CC ≤ 13.5 V
Room
Room
Room
Room
Room
Room
Room
Room
Room
3.96
60
0.7
0.12
50
4.00
25
± 15
80
1
1000
- 2.0
0.15
70
4.04
500
± 40
2000
- 1.4
V
nA
mV
dB
MHz
Ω
mA
dB
Current Limit
Threshold Voltage
Delay to Output
V SOURCE
t d
R L = 100 Ω from DRAIN to V CC
V FB = 0 V
R L = 100 Ω from DRAIN to V CC
V SOURCE = 1.5 V, See Figure 1
Room
Room
1.0
1.2
100
1.4
200
V
ns
Pre-Regulator/Start-Up
Input Voltage
Input Leakage Current
+ V IN
+ I IN
I IN = 10 μA
V CC ≥ 10 V
Room
Room
120
10
V
μA
Pre-Regulator Start-Up Current
V CC Pre-Regulator Turn-Off
Threshold Voltage
I START
V REG
Pulse Width ≤ 300 μs, V CC = 7 V
I PRE-REGULATOR = 10 μA
Room
Room
8
7.8
15
9.4
9.8
mA
Undervoltage Lockout
V UVLO
R L = 100 Ω from DRAIN to V CC
See Detailed Description
Room
7.0
8.8
9.3
V
V REG - V UVLO
V DELTA
Room
0.3
0.6
Supply
Supply Current
Bias Current
I CC
I BIAS
Room
Room
0.45
10
0.6
15
1.0
20
mA
μA
Logic
Latching Pulse Width
SHUTDOWN Delay e
SHUTDOWN Pulse Width e
RESET Pulse Width e
e
SHUTDOWN and RESET Low
t SD
t SW
t RW
t LW
V SOURCE = - V IN , See Figure 2
See Figure 3.
Room
Room
Room
Room
50
50
25
50
100
ns
Input Low Voltage
Input High Voltage
V IL
V IH
Room
Room
8.0
2.0
V
Input Current Input Voltage High
Input Current Input Voltage Low
I IH
I IL
V IN = V CC
V IN = 0 V
Room
Room
- 35
1
- 25
5
μA
MOSFET Switch
Breakdown Voltage
V BR(DSS)
I DRAIN = 100 μA
Full
200
220
V
Drain-Source On Resistance g
Drain Off Leakage Current
r DS(on)
I DSS
I DRAIN = 100 mA
V DRAIN = 150 V
Room
Room
3
5
5
10
Ω
μA
Drain Capacitance e
C DS
Room 35 pF
Notes:
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. C STRAY at OSC IN ≤ 5 pF.
g. Temperature coefficient of r DS(on) is 0.75 % per °C, typical.
Document Number: 70002
S-60752-Rev. E, 05-Apr-99
www.vishay.com
3
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