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参数资料
| 型号： | SI9105DN02-T1-E3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 3/11页 |
| 文件大小： | 0K |
| 描述： | IC REG FLYBK ISOLATED 4V 20PLCC |
| 标准包装： | 1,000 |
| 类型： | 回扫，隔离 |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 4V |
| 输入电压： | 10 V ~ 120 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 40kHz ~ 1MHz |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-LCC（J 形引线） |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 20-PLCC（9x9） |
Product is End of Life 3/2014
Si9105
Vishay Siliconix
SPECIFICATIONS a
Test Conditions
Unless Otherwise Specified
DISCHARGE = - V IN = 0 V
Limits
Parameter
Symbol
V CC = 10 V, + V IN = 48 V
R BIAS = 820 k Ω , R OSC = 910 k Ω
Temp b
Min c
Typ d
Max c
Unit
Error Amplifier
Open Loop Voltage Gain
Feedback Input Voltage
Input BIAS Current
Input OFFSET Voltage
Unity Gain Bandwidth e
e
V FB
I FB
A VOL
V OS
BW
FB Tied to COMP
OSC IN = - V IN (OSC Disabled)
OSC IN = - V IN , V FB = 4 V
OSC IN = - V IN (OSC Disabled)
OSC IN = - V IN
Room
Room
Room
Room
Room
3.96
60
0.5
4
25
80
± 15
0.8
4.04
500
± 40
V
nA
dB
mV
MHz
Dynamic Output Impedance
Z OUT
Room
1
k Ω
Output Current
Power Supply Rejection
I OUT
PSRR
Source (V FB = 3.4 V)
Sink (V FB = 4.5 V)
10 V ≤ V CC ≤ 13.5 V
Room
Room
Room
0.05
- 1.2
0.08
70
- 0.32
mA
dB
Current Limit
Threshold Voltage
Delay to Output e
V SOURCE
t d
R L = 100 Ω from DRAIN to V CC
V FB = 0 V
R L = 100 Ω from DRAIN to V CC
V SOURCE = 1.5 V, See Figure 1
Room
Room
0.8
1.0
200
1.2
300
V
ns
Input Voltage
Input Leakage Current
+ V IN
+ I IN
I IN = 10 μA
V CC ≥ 10 V
Room
Room
120
10
V
μA
Pre-Regulator Start-Up Current
V CC Pre-Regulator
Turn-Off Threshold Voltage
I START
V REG
Pulse Width ≤ 300 μs, V CC = 7 V
I PRE-REGULATOR = 10 μA
Room
Room
8
7.5
15
9.3
9.7
mA
Undervoltage Lockout
V UVLO
R L = 100 Ω from DRAIN to V CC
See Detailed Description
Room
7.0
8.7
9.2
V
V REG - V UVLO
V DELTA
Room
0.25
0.5
Supply
Supply Current
Bias Current
I CC
I BIAS
Room
Room
0.35
7.5
0.5
mA
μA
SHUTDOWN Delay
SHUTDOWN Pulse Width
RESET Pulse Width
Latching Pulse Width
SHUTDOWN and RESET Low
t SD
t SW
t RW
t LW
V SOURCE = - V IN , See Figure 2
See Figure 3
Room
Room
Room
Room
50
50
25
50
100
ns
Input Low Voltage
Input High Voltage
V IL
V IH
Room
Room
8.0
2.0
V
Input Current Input Voltage High
Input Current Input Voltage Low
I IH
I IL
V IN = 10 V
V IN = 0 V
Room
Room
- 35
1
- 25
5
μA
MOSFET Switch
Breakdown Voltage
V (BR)DSS
I DRAIN = 100 μA
Full
200
220
V
Drain-Source On Resistance g
Drain Off Leakage Current
r DS(on)
I DSS
I DRAIN = 100 mA
V DRAIN = 100 V
Room
Room
5
7
10
Ω
μA
Drain Capacitance
C DS
Room 35 pF
Notes:
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Guaranteed by design, not subject to production test.
f. C STRAY Pin 8 = ≤ 5 pF.
g .Temperature coefficient of r DS(on) is 0.75 % per °C, typical.
Document Number: 70003
S-70497-Rev. I, 19-Mar-07
www.vishay.com
3
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