参数资料
| 型号： | SI9110DJ-E3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 3/9页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR FLYBK CUK CM 14PDIP |
| 标准包装： | 500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 3MHz |
| 占空比： | 50% |
| 电源电压： | 9.5 V ~ 13.5 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 是 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 14-DIP（0.300"，7.62mm） |
| 包装： | 散装 |
Si9110, Si9111
Vishay Siliconix
SPECIFICATIONS a
Test Conditions
D Suffix
Parameter
Symbol
Unless Otherwise Specified
DISCHARGE = - V IN = 0 V
V CC = 10 V, + V IN = 48 V
R BIAS = 390 k ? , R OSC = 330 k ?
Temp. b
- 40 °C to 85 °C
Min. d Typ. c Max. d
Unit
Error Amplifier
Feedback Input Voltage
Input BIAS Current
V FB
I FB
FB Tied to COMP
OSC IN = - V IN , (OSC Disabled)
OSC IN = - V IN , V FB = 4 V
Si9110
Si9111
Room
Room
Room
3.96
3.60
4.00
4.00
25
4.04
4.40
500
V
nA
Input OFFSET Voltage
V OS
Room
± 15
± 40
mV
Open Loop Voltage Gain e
A VOL
OSC IN = - V IN
Room
60
80
dB
Unity Gain Bandwidth
e
BW
(OSC Disabled)
Room
1
1.3
MHz
Dynamic Output Impedance e
Z OUT
Room
1000
2000
?
Output Current
Power Supply Rejection
I OUT
PSRR
Source (V FB = 3.4 V)
Sink (V FB = 4.5 V)
9.5 V ? V CC ? 13.5 V
Room
Room
Room
0.12
50
- 2.0
0.15
70
- 1.4
mA
dB
Current Limit
Delay to Output
Threshold Voltage
e
V SOURCE
t d
V FB = 0
V SENSE = 1.5 V, See Figure 1
Room
Room
1.0
1.2
100
1.4
150
V
ns
Pre-Regulator/Start-Up
Input Voltage
Input Leakage Current
+ V IN
+ I IN
I IN = 10 μA
V CC ? 9.4 V
Room
Room
120
10
V
μA
Pre-Regulator Start-Up Current
V CC Pre-Regulator Turn-Off
Threshold Voltage
I START
V REG
Pulse Width ? 300 μs, V CC = V ULVO
I PRE-REGULATOR = 10 μA
Room
Room
8
7.8
15
8.6
9.4
mA
Undervoltage Lockout
V REG - V UVLO
V UVLO
V DELTA
Room
Room
7.0
0.3
8.1
0.6
8.9
V
Supply
Supply Current
Bias Current
I CC
I BIAS
V LOAD ? 75 pF (Pin 4)
Room
Room
0.45
10
0.6
15
1.0
20
mA
μA
Logic
SHUTDOWN Delay e
SHUTDOWN Pulse Width e
RESET Pulse Width e
Latching Pulse Width
SHUTDOWN and RESET Low e
t SD
t SW
t RW
t LW
C L = 500 pF, V SENSE = - V IN , See Figure 2
See Figure 3
See Figure 3
Room
Room
Room
Room
50
50
25
50
100
ns
Input Low Voltage
Input High Voltage
V IL
V IH
Room
Room
8.0
2.0
V
Input Current Input Voltage High
Input Current Input Voltage Low
I IH
I IL
V IN = 10 V
V IN = 0 V
Room
Room
- 35
1
- 25
5
μA
Output
Fall Time
Output High Voltage
Output Low Voltage
Output Resistance
Rise Time e
e
V OH
V OL
R OUT
t r
t f
I OUT = - 10 mA
I OUT = 10 mA
I OUT = 10 mA, Source or Sink
C L = 500 pF
Room
Full
Room
Full
Room
Full
Room
Room
9.7
9.5
20
25
40
40
0.30
0.50
30
50
75
75
V
?
ns
Notes:
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
e. Guaranteed by design, not subject to production test.
f. C STRAY Pin 8 = ? 5 pF.
Document Number: 70004
S11-0975-Rev. I, 16-May-11
www.vishay.com
3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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