参数资料
| 型号： | SI9150DY-E3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 5/8页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 14-SOIC |
| 标准包装： | 550 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 345kHz |
| 占空比： | 100% |
| 电源电压： | 5.7 V ~ 18 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 包装： | 散装 |
Product is End of Life 3/2014
Si9150
Vishay Siliconix
PIN CONFIGURATION AND ORDERING INFORMATION
SOIC
ORDERING INFORMATION
EN
1
14
V DD
Part Number
Temperature Range
Package
STANDBY
SS
COMP
FB
V REF
I SENSE
2
3
4
5
6
7
13
12
11
10
9
8
P-GATE
N-GATE
GND
R T
C T
SYNC
Si9150CY
Si9150CY-T1
Si9150CY-T1-E3
Si9150DY
Si9150DY-T1
Si9150DY-T1-E3
0 to 70 °C
- 40 to 85 °C
SOIC-14
Top View
PIN DESCRIPTION
Pin 1: EN
When this pin is low, the IC is shut down. After a low signal
is applied to EN, then COMP, REF, R T , and C T settle toward
ground; N-GATE, STBY and Soft-Start are grounded; and P-
GATE is pulled high. The current consumption is no more
than 100 μA in this state. This input’s threshold has substan-
tial hysteresis so that a capacitor to GND can be used to
delay restart after the current limit is activated. After V ENH is
exceeded, one clock cycle elapses before N-GATE and P-
GATE are enabled. EN is pulled up to V DD through a 500 k
resistor and is pulled down internally when the current limit is
triggered.
Pin 2: STBY
Has a function similar to EN. The differences are that the EN
pin is unaffected, that the reference is still available, that bias
currents are still present internally, and that this pin’s pull up
current is present. This pin should be used to disable an
application if the reference voltage is still needed.
Pin 3: Soft-Start (SS)
This pin limits the maximum voltage that the error amplifier
can output. A capacitor between this pin and ground will limit
the rate at which the duty factor can increase during initial
power up, during a restart when EN or STBY goes high, or
after the current limit is triggered. A capacitor here can pre-
vent an application from triggering the Si9150’s current limit
during startup. Soft-Start is pulled low if either EN or STBY is
low.
Pin 4: Compensation (COMP)
This pin is tied directly to the output of the error amplifier. The
feedback network which insures the stability of an application
uses this pin. COMP settles low when either EN or STBY is
pulled low.
Document Number: 70020
S-40752-Rev. F, 19-Apr-04
Pin 5: Feedback (FB)
This pin is attached directly to the inverting input of the error
amplifier. This pin is used to regulate the power supply’s out-
put voltage.
Pin 6: Reference (V REF )
The internal 2.5 V reference generator is attached to this pin
through a 5 Ω resistor. A 0.1 μF bypass capacitor is needed
to suppress noise. Also note that the generator has an open
emitter; it will not pull down. The maximum current that the
generator will source before it current limits is about 10 mA.
Many parts of the IC use this voltage, so it is important not to
overload the reference generator.
Pin 7: I SENSE
This pin should be attached to the switched node (the
drains of the application’s P-Channel and N-Channel MOS-
FETs). If the voltage between V DD and this pin is more then
0.46 V while the P-GATE is low, the current limit is acti-
vated. The current limit is relatively slow to prevent false
triggering due to noise. Activating the current limit causes
EN to be pulled to GND. I SENSE may be operated from V DD
+ 2 V to GND - 2 V. For operation above 13.5 V DD a filter
(1 k Ω , 33 pF) is needed between the MOSFET drains and
the I SENSE pin; refer to Figure 1.
Pin 8: SYNC
This pin forces the clock to reset when low, and is also pulled
low when the clock resets itself. Thus if several Si9150’s
have their sync pins shorted together, they will be synchro-
nized; the shortest duration clock will control the other
clocks.
www.vishay.com
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