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参数资料
| 型号： | SI9947DY |
| 英文描述： | Dual P-Channel Enhancement-Mode MOSFET |
| 中文描述： | 双P沟道增强型MOSFET |
| 文件页数： | 2/4页 |
| 文件大小： | 87K |
| 代理商： | SI9947DY |
Si9947DY
2
Siliconix
S-47958—Rev. F, 15-Apr-96
Specifications (T
J
= 25 C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
Typ
a
Max
Unit
Static
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
= –250 A
–1.0
V
Gate-Body Leakage
I
GSS
V
DS
= 0 V, V
GS
=
20 V
100
nA
Zero Gate Voltage Drain Current
I
DSS
V
DS
= –16 V, V
GS
= 0 V
–1
A
V
DS
= –10 V, V
GS
= 0 V, T
J
= 70 C
–5
On-State Drain Current
b
I
D(on)
V
DS
–5 V, V
GS
= –10 V
–14
A
V
DS
–5 V, V
GS
= –4.5 V
–2.5
Drain-Source On-State Resistance
b
r
DS(on)
V
GS
= –10 V, I
D
= 3.5 A
0.10
V
GS
= –4.5 V, I
D
= 2 A
0.19
Forward Transconductance
b
g
fs
V
DS
= –15 V, I
D
= –3.5 A
4.0
S
Diode Forward Voltage
b
V
SD
I
S
= –1.7 A, V
GS
= 0 V
–0.9
–1.2
V
Dynamic
a
Total Gate Charge
Q
g
13
30
Gate-Source Charge
Q
gs
V
DS
= –10 V,
V
GS
= –10 V, I
D
= –3.5 A
2
nC
Gate-Drain Charge
Q
gd
5
Turn-On Delay Time
t
d(on)
21
40
Rise Time
t
r
V
= –10 V,
= 10
1 A V
–1 A, V
GEN
= –10 V, R
G
= 6
I
D
10 V R
12
25
Turn-Off Delay Time
t
d(off)
DD
L
12
30
ns
Fall Time
t
f
11
20
Source-Drain Reverse Recovery Time
t
rr
I
F
= –3.5 A, di/dt = 100 A/ s
50
100
Notes
a.
b.
Guaranteed by design, not subject to production testing.
Pulse test; pulse width
300 s, duty cycle
2%.
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