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参数资料
| 型号： | SIP11206DQP-T1-E3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 9/19页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR ISO PWM 16-TSSOP |
| 标准包装： | 3,000 |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 占空比： | 50% |
| 电源电压： | 10.5 V ~ 13.2 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 带卷 (TR) |
SiP11206
Vishay Siliconix
If an MOC fault occurs following the start-up (due to a
condition such as an excessive load on the converter’s
output), SiP11206 will respond by gradually reducing the
available maximum duty cycle of its DL and DH outputs each
to be equal to approximately 42 % of their possible 47 %
maximum values. This is before any effects of deadtime
introduced by R DB are added in. This reduction in available
maximum duty cycle is achieved by reducing the voltage on
the SS pin to 4 V, as follows:
1. If V MOC < V CS < V SOC at any time during T DL , a current
of 20 μA will be drawn out of the SS pin until the
beginning of the next T DL .
2. If the voltage on the SS pin remains above the value that
would allow an available maximum DL and DH duty cycle
of 42 %, SiP11206 will continue operating.
3. If the voltage on the SS pin goes below the value that
would allow an available maximum DL and DH duty cycle
of 42 %, a hiccup interval is started, during which both DL
and DH are held in their low states.
4. The SS pin is discharged towards 0 V by a 400 nA sink
current.
5. The hiccup interval is terminated when the SS pin is
discharged to 0.25 V.
After the above actions have been taken switching on the DL
and DH outputs will then resume with a normal soft-start
cycle.
Response to MOC faults is enabled after the successful
completion of any normal soft-start cycle.
Response to SOC Faults (V CS > V SOC ):
This is an immediate, single-cycle response over current
shutdown, followed by a hiccup delay and a normal soft-start
cycle. Since this is a gross fault protection mechanism, its
triggering mechanism is asynchronous to the timing of T DL
and T DH .
1. If V CS > V SOC , a hiccup interval is started, during which
both DL and DH are held in their low states.
2. The SS pin is discharged towards 0 V by a 400 nA sink
current.
3. The hiccup interval is terminated when the SS pin is
discharged to 0.25 V.
4. Switching on the DL and DH outputs will then resume
with a normal soft-start cycle.
Severe over current response is enabled at all times,
including the initial ramp-up period of the soft-start pin. This
allows SiP11206 to provide rapid fault protection for the
converter’s power train.
Immediate Response to UVLO Faults:
The under voltage protection conditions at converter-level
(V INDET pin UVLO) and chip-level (V CC UVLO) will
immediately trigger a shutdown-and-retry SS response, with
the restart requirements being that:
Document Number: 69232
S-81795-Rev. C, 04-Aug-08
1. The SS pin has been discharged at a 20 μA rate to the
0.25 V level.
2. The affected supply has recovered to its turn-on
threshold.
Once these conditions are met, switching will resume with a
normal soft-start cycle. Response to UVLO faults is enabled
at all times, including the initial ramp-up period of the soft-
start pin.
Immediate Response to an OTP Condition:
Failure of the application circuit to provide an external
voltage to the V CC pin above the V REG level may result in an
OTP condition (T J > OTP ON ). Other conditions, such as
excessive ambient temperature or, where applicable, failure
of airflow over the DC-DC converter circuit, can also trigger
an OTP condition. An OTP condition will immediately trigger
a shutdown-and-retry soft start response, with the restart
requirements being that:
1. The SS pin has been discharged at a 20 μA rate to the
0.25 V level.
2. The chip junction temperature has fallen below the lower
OTP threshold.
Once these conditions are met, switching will resume with a
normal soft-start cycle. Response to the OTP condition is
enabled at all times, including the initial ramp-up period of the
soft-start pin.
Reference
The reference voltage of SiP11206 is set at 3.3 V at V REF
pin. This pin should be decoupled externally with a 0.1 μF to
1 μF capacitor to GND. Up to 5 mA may be drawn internally
from this reference to power external circuits. Note that if the
V INDET pin is pulled below 0.55 V (typical), the reference will
be turned off, and SiP11206 will enter a low-power "standby"
mode. During startup or when V REF is accidentally shorted to
ground, this pin has internal short circuit protection limiting
the source current to 50 mA. V REF load regulation for 5 mA
step is typically 0.45 %.
Oscillator
The oscillator is designed to operate from 200 kHz to 1 MHz
with temperature stability within 15 %. This operating
frequency range allows the converter to minimize the
inductor and capacitor size, improving the power density of
the converter. The oscillator frequency, and therefore the
switching frequency, is programmable by the value of
resistor and capacitor connected to the R OSC and C OSC pins
respectively. Note that the switching frequency at pins DL
and DH is half of the oscillator frequency, i.e., the DL output
will be active during one oscillator cycle, and the DH during
the next oscillator cycle.
V INDET
The V INDET pin controls several modes of operation and the
modes of operation are controlled by shutdown (V SD ) and
under voltage (V UV ) comparators (see block diagram). When
the IC is powered solely by V IN and V INDET is less than V SDH
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