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| 型号： | SIP12506DMP-T1-E3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 7/13页 |
| 文件大小： | 0K |
| 描述： | IC REG BOOST ADJ 1.6A MLP33-6 |
| 标准包装： | 3,000 |
| 类型： | 升压（升压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 20V |
| 输入电压： | 2.6 V ~ 9 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 1.6A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | PowerPAK? MLP33-6 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | PowerPAK? MLP33-6 |
Product is End of Life 3/2014
SiP12506
Vishay Siliconix
DIODE SELECTION:
A schottky diode is recommended for use as the external rec-
tifier. Schottky diodes are typically preferred in DC-DC con-
version applications because of their low forward voltage
drop and fast recovery time, which allows for high frequency
DUTY CYCLE CALCULATION:
In continuous mode of operation, the maximum duty cycle of
a boost switching regulator determines the maximum
amount of boost (V OUT /V IN ) attainable and can be calculated
using the expression
switching. In choosing a diode, ensure that the diode's
reverse breakdown voltage exceeds the intended V OUT of
design and that its current rating is greater then the peak
inductor current. For applications in which less than 0.5 A of
D (MAX) =
V OUT + V Diode - V IN
V OUT + V Diode - V SW
average output current is required and output voltage is less
than 15 V, a diode such as the MBR0520 is recommended.
For V OUTs higher than 15 V, a 30 V diode such as the
Where V Diode is the forward bias voltage of the schottky
diode and Vsw denotes the voltage drop across the internal
switch and can be expressed as
MBR0530 should be considered.
V SW = R DS(on) x I L(PEAK)
INPUT CAPACITOR SELECTION:
The input bypass capacitor acts as an energy reservoir that
satisfies the transient inductor current needs each time the
switch turns on. In effect, the input capacitor is responsible
for reducing the input voltage ripple and the amount of EMI
that is inevitably passed to other circuitry on that line. For this
purpose, a 4.7 μF ceramic capacitor is recommended. If pre-
The above equation yields only an approximation of the duty
cycle since it ignores power loss terms resulting from wire
losses in the inductor, switching losses of the internal FET,
and capacitor ripple current losses due to their inherent non-
zero ESR. A more accurate estimate of the duty cycle can be
determined by
ferred, tantalum capacitors may be used instead of ceramics.
OUTPUT CAPACITOR SELECTION:
D = 1 - Efficiency x
V I N
V OUT
To curb output voltage ripple, a multi-layer ceramic capacitor
should be used as the output filter capacitor. Ceramic capac-
itors are favored for their low ESR (equivalent series resis-
tance) and high resonance frequency which makes them
ideal for high frequency switching converters. A high ESL
(equivalent series inductance) can give rise to ringing in the
low megahertz region and a high ESR could reduce phase
margin and potentially cause instability of the design. In addi-
tion, the ripple current flowing through the capacitor's ESR
causes power dissipation and heats up the capacitor inter-
nally. If the ripple current ratings of the capacitor are
exceeded, the excessive temperature could shorten the
expected life of the capacitor.
If a high value capacitor is required for improved transient
And by using the provided efficiency curves to approximate
efficiency for a given input and output voltage.
INDUCTOR SELECTION:
An inductor is one of the energy storage components in a
converter. Choosing an inductor means specifying its size,
structure, material, inductance, saturation level, DC-resis-
tance (DCR), and core loss. Choosing the right inductor is
not a simple task and involves tradeoffs in performance. The
following are some key parameters that should be focused
on. In PWM mode, inductance has a direct impact on the rip-
ple current. The peak-to-peak inductor ripple current can be
calculated as
response, to keep component costs down and to save PC
board real estate, tantalum capacitor may be used in parallel
with ceramics. If the maximum tolerated ripple current (I P-P )
and ripple voltage ( Δ V O ) design specifications are known,
I p ? p =
D × ( V I N ? V s w )
L × f s w
the maximum tolerated ESR on the output capacitor and its
value can be calculated using the following formulas:
Where Vsw is the voltage drop across the switch in its on
state, fsw is the switching frequency, and D is the duty cycle.
? ?
× I OUT (MAX) + P-P ? ?
ESR (MAX) =
? 1
? 1 - D MAX
Δ V OUT
I ?
2 ?
Higher inductance means lower ripple current, lower rms cur-
rent, lower voltage ripple on both input and output, and
higher efficiency, unless the resistive loss of the inductor
dominates the overall conduction loss. However, higher
inductance also means a larger inductor size and a slower
C OUT (MIN) =
I OUT (MAX) × D MAX
f SW × Δ V OUT
transient response. For fixed line, load, and frequency condi-
tions, higher inductance results in a lower peak current for
each pulse and a higher load capability.
The saturation current is another important parameter in
Where I OUT (MAX) is the maximum output current and D MAX
represents the maximum duty cycle.
Document Number: 73861
S-70547–Rev. D, 26-Mar-07
choosing inductors. Note that the saturation levels specified
in data sheets are maximum currents. For a DC-DC con-
verter operating in PWM mode, it is the maximum peak
inductor current that is relevant, and which can be calculated
using these equations:
www.vishay.com
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