参数资料
| 型号： | SIP21107DT-12-E3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 14/19页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 1.2V .15A TSOT23-5 |
| 标准包装： | 3,000 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 1.2V |
| 输入电压： | 2.2 V ~ 6 V |
| 稳压器数量： | 1 |
| 电流 - 输出： | 150mA |
| 电流 - 限制（最小）： | 170mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-5 细型，TSOT-23-5 |
| 供应商设备封装： | TSOT-23-5 |
| 包装： | 带卷 (TR) |
SiP21106, SiP21107, SiP21108
Vishay Siliconix
POK Status in SiP21107
The POK comparator monitors the output until the supply
comes up to specified percentage of V IN . This open drain
NMOS output requires an external pull-up resistor to either
V OUT or V IN . The internal NMOS can drive up to 0.5 mA
loads. POK pin is active high to indicate that output is within
percentage tolerance. POK goes low when output is outside
The GND pin of the SiP2110 acts as both the electrical
connection to GND as well as a path for channeling away
heat. Connect this pin to a GND plane to maximize heat
dissipation. Once maximum power dissipation is calculated
using the equation above, the maximum allowable output
current for any input/output potential can be calculated as
of this tolerance as when in dropout, over current and
thermal shutdown.
I OUT(max) =
P (max)
V I N - V OUT
APPLICATION INFORMATION
Input/Output Capacitor Selection and Regulator Stability
It is recommended that a low ESR 1 μF capacitor be used on
the SiP21106, SiP21107, SiP21108 input. A larger input
capacitance with lower ESR would improve noise rejection
and line-transient response. A larger input bypass capacitor
may be required in applications involving long inductive
traces between the source and LDO. The circuit is stable with
only a small output capacitor equal to 6 nF/mA ( ≈ 1 μF at
150 mA) of load. Since the bandwidth of the error amplifier is
around 1 MHz - 3 MHz and the dominant pole is at the output
node, the capacitor should be capacitive in this range, i.e., for
150 mA load current, an ESR < 0.4 Ω is necessary. Parasitic
inductance of about 10 nH can be tolerated. Applying a larger
output capacitor would increase power supply rejection and
improve load-transient response. Some ceramic dielectrics
such as the Z5U and Y5V exhibit large capacitance and ESR
variation over temperature. If such capacitors are used, a
2.2 μF or larger value may be needed to ensure stability over
the industrial temperature range. If using higher quality
ceramic capacitors, such as those with X7R and Y7R
dielectrics, a 1 μF capacitor will be sufficient at all operating
temperatures.
Operating Region and Power Dissipation
An important consideration when designing power supplies
is the maximum allowable power dissipation of a part. The
maximum power dissipation in any application is dependant
on the maximum junction temperature, T J(max) = 125 °C, the
ambient temperature, T A , and the junction-to-ambient
thermal resistance for the package, which is the summation
of θ J-C , the thermal resistance of the package, and θ C-A , the
thermal resistance through the PC board and copper traces.
Power dissipation may be expressed as:
PCB Layout
The component placement around the LDO should be done
carefully to achieve good dynamic line and load response.
The input and noise capacitor should be kept close to the
LDO. The rise in junction temperature depends on how
efficiently the heat is carried away from junction-to-ambient.
The junction-to-lead thermal impedance is a characteristic of
the package and is fixed. The thermal impedance between
lead-to-ambient can be reduced by increasing the copper
area on PCB. Increase the input, output and ground trace
area to reduce the junction-to-ambient thermal impedance.
P (max) =
T J (max) - T A
θ J-C + θ C-A
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?74442 .
www.vishay.com
14
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SIP21107DT-18-E3 | 功能描述:低压差稳压器 - LDO Low Noise 150mA 1.8V RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| SIP21107DT-25-E3 | 功能描述:低压差稳压器 - LDO Low Noise 150mA 2.5V RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| SIP21107DT-26-E3 | 功能描述:低压差稳压器 - LDO Low Noise 150mA 2.6V RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| SIP21107DT-285-E3 | 功能描述:低压差稳压器 - LDO Lo Noise 150mA 2.85V RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| SIP21107DT-28-E3 | 功能描述:低压差稳压器 - LDO Low Noise 150mA 2.8V RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
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