参数资料
型号: SK100EL15WU
元件分类: 时钟及定时
英文描述: 100EL SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), UUC
封装: DIE
文件页数: 1/4页
文件大小: 65K
代理商: SK100EL15WU
HIGH-PERFORMANCE PRODUCTS
1
www.semtech.com
Revision 1/August 23, 2001
SK10/100EL15W
1:4 Clock
Distribution
Description
Features
Functional Block Diagram
The SK10/100EL15W is a low skew 1:4 clock distribution
chips designed explicitly for low skew clock distribution
applications.
This device is fully compatible with
MC10EL15 & MC100EL15. The device can be driven by
either a differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. If a single-ended
input is to be used, the VBB output should be connected
to the CLK* input and bypassed to VCC via a 0.01 F
capacitor. The EL15W provides a VBB output for either
single-ended use or as a DC bias for AC coupling to the
device. The VBB pin should be used only as a bias for
EL15W as its current sink/source capability is limited.
Whenever used, the VBB pin should be bypassed to VCC
via a 0.01 F capacitor.
The EL15W features a multiplexed clock input to allow for
the distribution of a lower speed scan or test clock along
with the high speed system clock. When LOW (or left
open and pulled LOW by the input pull-down resistor) the
SEL pin will select the differential clock input.
The common enable (EN*) is synchronous so that the
outputs will only be enabled/disabled when they are already
in the LOW state. This avoids any chance of generating a
runt clock pulse when the device is enabled/disabled as
can happen with an asynchronous control. The internal
flip-flop is clocked on the falling edge of the input clock,
therefore, all associated specification limits are referenced
to the negative edge of the clock input.
Extended Supply Voltage Range: (VEE = –5.5V to
–3.0V, VCC = 0V) or (VCC = + 3.0V to +5.5V,
VEE=0V)
50 ps Output-to-Output Skew
Synchronous Enable/Disable
Multiplexed Clock Input
Internal 75K
W Input Pull-Down Resistors
Fully Compatible with MC10/100EL15
Specified Over Industrial Temperature Range:
–40oC to +85oC
ESD Protection of >4000V
Available in 16 Lead SOIC Package
PIN Description
e
m
a
N
n
i
Pn
o
i
t
c
n
u
F
K
L
Cs
t
u
p
n
I
k
c
o
l
C
l
a
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t
n
e
r
e
f
i
D
K
L
C
St
u
p
n
I
k
c
o
l
C
s
u
o
n
o
r
h
c
n
y
S
*
N
Ee
l
b
a
n
E
s
u
o
n
o
r
h
c
n
y
S
L
E
St
u
p
n
I
t
c
e
l
e
S
k
c
o
l
C
V B
B
e
g
a
t
l
o
V
t
u
p
t
u
O
e
c
n
e
r
e
f
e
R
*
3
Q
-
*
0
Q
,
3
Q
0
Qs
t
u
p
t
u
O
k
c
o
l
C
l
a
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t
n
e
r
e
f
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D
K
L
CK
L
C
SL
E
S*
N
EQ
L
X
LLL
HX
L
H
XL
H
L
XH
H
L
H
XXX
H
*
L
Truth Table
*On next negative transition of CLK or SCLK.
Q0
Q0*
Q2
Q2*
Q3
Q3*
Q1
Q1*
V
CC
EN*
CLK*
VBB
SEL
VEE
SCLK
CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q
D
1
0
相关PDF资料
PDF描述
SK100EL15WD 100EL SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
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