参数资料
型号: SK10E151PJ
元件分类: 锁存器
英文描述: 10E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC28
封装: PLASTIC, LCC-28
文件页数: 1/5页
文件大小: 94K
代理商: SK10E151PJ
HIGH-PER.ORMANCE PRODUCTS
1
www.semtech.com
Revision 2/ March 27, 2002
SK10/100E151
6-Bit D Register
Description
.eatures
.unctional Block Diagram
Pin Description
The SK10/100E151 offers 6 edge-triggered, high-speed,
master-slave D-type flip-flops with differential outputs,
designed for use in new high-performance ECL systems.
This device is fully compatible with MC10E151 and
MC100E151. The two external clock signals (CLK1, CLK2)
are gated through a logical OR operation before use as
clocking control for the flip-flops. Data is clocked into
the flip-flops on the rising edge of either CLK1 or CLK2
(or both).
When both CLK1 and CLK2 are at a logic
LOW, data enters the master and is transferred to the
slave when either CLK1 or CLK2 (or both) go HIGH.
The MR (Master Reset) signal operates asynchronously
to make all Q outputs go to a logic LOW.
1100 MHz Toggle Frequency
Extended 100E VEE Range of –4.2V to –5.5V
Differential Outputs
Asynchronous Master Reset
Dual Clocks
Internal 75K
Input Pulldown Resistors
ESD Protection of >4000V
Fully Compatible with MC10/100E151
Specified Over Industrial Temperature Range:
–40oC to +85oC
Available in 28-Pin PLCC Package
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Q0
D0
Q0*
R
D
Q1
D1
Q1*
R
D
Q2
D2
Q2*
R
D
Q3
D3
Q3*
R
D
Q4
D4
Q4*
R
D
Q5
D5
CLK1
CLK2
MR
Q5*
R
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25
24
23
22
21
20
19
MR
CLK2
CLK1
NC
VCC0
Q5*
Q5
Q4*
Q4
VCC
Q3*
Q3
Q2*
Q2
D5
D4
D3
VEE
D2
D1
D0
NC
VCC0
Q0
Q0*
Q1
Q1*
VCC0
5
6
7
8
9
10
11
PLCC
TOP VIEW
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