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参数资料
| 型号： | SK10EL34WD |
| 元件分类： | 时钟及定时 |
| 英文描述： | 10EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | SOIC-16 |
| 文件页数： | 1/6页 |
| 文件大小： | 82K |
| 代理商： | SK10EL34WD |
HIGH-PERFORMANCE PRODUCTS
1
www.semtech.com
Revision 1/November 7, 2001
SK10/100EL34W
÷2, ÷4, ÷8 Clock Generation Chip
Description
Features
Functional Block Diagram
The SK10/100EL34W are low skew, ÷2, ÷4, ÷8 clock
generation chips designed explicitly for low skew clock
generation applications.
The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned.
This device is fully
compatible with On-Semiconductor’s MC10EL34 and
MC100EL34. These devices can be driven by either a
differential or single-ended ECL or, if positive power supplies
are used, PECL input signal. In addition, by using the
VBB output, a sinusoidal source can be AC-coupled into
the device. The EL34W provides a VBB output for single-
ended use or DC bias for AC coupling to the device. VBB
is an output pin and should be used as a bias for the
EL34W as its current source/sink capability is limited up
to 0.5 mA. Whenever used, the VBB output should be
bypassed to VCC via a 0.01 F capacitor.
The common enable (EN*) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids any
chance of generating a runt clock pulse on the internal
clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could
lead to losing synchronization between the internal
divider stages. The internal enable flip-flop is clocked
on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple EL34Ws in a system.
Extended Supply Voltage Range: (VEE = –3.0V to
–5.5V, VCC = 0V) or (VCC = +3.0V to +5.5V,
VEE = 0V)
50 ps Output-to-Output Skew
VBB Output
Synchronous Enable/Disable
Master Reset for Synchronization
Internal 75K
W Input Pull-Down Resistors
Fully Compatible with MC10EL34 and
MC100EL34
Specified Over Industrial Temperature Range:
–40oC to 85oC
ESD Protection of >4000V
Available in 16-Pin SOIC Package
Q0
Q0*
Q1*
VCC
Q2
Q2*
VCC
Q1
VCC
EN*
CLK*
VBB
MR
VEE
NC
CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
÷ 2
R
Q
R
Q
D
÷ 8
R
Q
÷ 4
R
Q
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| SK100EL58DT | 100EL SERIES, 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO8 |
| SK10EL58D | 10EL SERIES, 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO8 |
| SK10LVEL58DT | 10LVEL SERIES, 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO8 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SK10ELT21W | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK10ELT21WD | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK10ELT21WDT | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK10ELT21WU | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK10EP111 | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver |
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