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参数资料
| 型号： | SL1461SA/KG/MPAS |
| 厂商： | INTEL CORP |
| 元件分类： | 通信及网络 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PDSO16 |
| 封装： | 0.150 INCH, MS-012AC, SOIC-16 |
| 文件页数： | 8/13页 |
| 文件大小： | 377K |
| 代理商： | SL1461SA/KG/MPAS |
4
SP1461SA Advance Information
41
250
°C/W
mW
kV
ABSOLUTE MAXIMUM RATINGS cont.
All voltages are referred to VEE at 0V
Min.
Typ.
Max.
MP16 package thermal resistance,
chip to case
Power consumption at 5.5V
ESD protection - pins 1 to 15
ESD protection - Pin 16
Conditions
Characteristics
2
1.7
Mil-std-883 method 3015 class 1
Fig.3 Standard application circuit
16
116
89
2
4
3
5
6
7
10
11
12
13
14
15
SL1461SA
2K
AGC BIAS
AFC WINDOW ADJUST
50K
27K
100nF
47 F
+5V
47nF
100nF
5K1
4n7
4K7
1nF
RF INPUT
1nF
47 F
1K2
4K7
VIDEO OUTPUT
470nF
BB515
100pF
RV1
RV2
R6
C3
C4
1nF
C12
C2
C1
R1
C11
TP1
TP2
C10
R5
R4
C9
C8
C7
R3
C6
TP3
D2
D1
C5
R2
TP4
FUNCTIONAL DESCRIPTION
The SL1461SA is a wideband PLL FM demodulator,
optimised for application in satellite receiver systems and
requiring a minimum external component count. It contains all
the elements required for construction of a phase locked loop
circuit, with the exception of tuning components for the local
oscillator, and an AFC detector circuit for generation of error
signal to correct for any frequency drift in the outdoor unit local
oscillator. A block diagram is contained in Fig. 2 and the
typical application in Fig. 3.
The internal pin connections are contained in Fig.6/6a
In normal applications the second satellite IF frequency
of typically 402 or 479.5MHz is fed to the RF preamplifier,
which has a working sensitivity of typically -40 dBm,
depending on application and layout. The preamplifier
contains an RF level detect circuit, which generates an AGC
signal that can be used for controlling the gain of the IF
amplifier stages, so maintaining a fixed level to the RF input
of the SL1461SA, for optimum threshold performance. The
bias point of the AGC circuit can be adjusted to cater for
variation in AGC line voltage requirement and device input
power. The typical AGC curves are shown in Fig. 9. It is
recommended that the device is operated with an input signal
between -30 and -35dBm. This ensures optimum linearity and
threshold performance, and gives a good safety margin over
the typical sensitivity of
-40dBm.
The output of the preamplifier is fed to the mixer section
which is of balanced design for low radiation. In this stage the
RF signal is mixed with the local oscillator frequency, which
is generatedby an on–board oscillator. The oscillator block
uses an external varactor tuned sustaining network and is
optimised for high linearity over the normal deviation range.
A typical frequency versus voltage characteristic for the
oscillator is contained in Fig. 7. The loop output is designed
to compensate for first order temperature variation effects;
the typical stability is shown in Fig. 8
The output of the mixer is then fed to the loop amplifier
around which feedback is applied to determine loop transfer
characteristic . Feedback can be applied either in differential
or single ended mode; if the appropriate phase detector gains
are assumed in calculating loop filters, both modes should
give the same loop response.
The loop amplifier drives a 75
output impedance buffer
amplifier, which can either be connected to a 75
load or used
to drive a high input impedance stage giving greater linearity
and approximately 6dB higher demodulated signal output
level.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SL1466 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Wideband PLL FM Demodulator |
| SL1466KG | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Wideband PLL FM Demodulator |
| SL1466QP1S | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Wideband PLL FM Demodulator |
| SL1496C | 制造商:PLW 功能描述:1496C 制造商:PSSB 功能描述:1496C |
| SL14B | 制造商:SR COMPONENTS 功能描述: 制造商:SR Components Inc 功能描述: |
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