Rev 2.0, May 28, 2008
Page 3 of 18
SL23EP08
General Description
The SL23EP08 is a low skew, low jitter Zero Delay
Buffer with very low operating current.
The product includes an on-chip high performance PLL
that locks into the input reference clock and produces
eight (8) output clock drivers tracking the input
reference clock for systems requiring clock distribution.
in addition to FBK pin used for internal PLL feedback,
there are two (2) banks with four (4) outputs in each
bank, bringing the number of total available output
clocks to eight (8).
Input and output Frequency Range
The input and output frequency range is the same for
SL23EP08-1 and -1H versions. For SL23EP08-2, -2H -
3, -4 and -5H versions, the output frequency is 1/2x,
1x, 2x, or 4x of the CLKIN as given in the “Available
SL23EP08 Configurations” Table 3. But, the frequency
range depends on VDD, drive levels and output load
(CL) as given in the “Electrical Specification” Tables.
If the input clock frequency is DC (from GND to VDD),
this is detected by an input frequency detection
circuitry and all eight (8) clock outputs are forced to Hi-
Z. The PLL is shutdown to save power. In this
shutdown state, the product draws less than 10 μA
supply current.
SpreadThru Feature
If a Spread Spectrum Clock (SSC) were to be used as
an input reference clock, the SL23EP08 is designed to
pass the modulated Spread Spectrum Clock (SSC)
signal from its reference input to the output clocks. The
same spread characteristics at the input are passed
through the PLL and drivers without any degradation in
spread percent (%), spread profile and modulation
frequency.
Select Input Control
The SL23EP08 provides two (2) input select control
pins called S1 and S2. This feature enables users to
selects various states of output clock banks-A and
bank-B, output source and PLL shutdown features as
shown in the Table 2.
The S1 (Pin-9) and S2 (Pin-8) inputs include 250 k
weak pull-down resistors to GND.
PLL Bypass Mode
If the S2=1 and S1=0, the on-chip PLL is shutdown and
bypassed, and all the eight (8) output clocks of bank A
and bank B are driven directly from the reference input
clock. In this operation mode SL23EP08 works like a
non-ZDB fanout buffer.
High and Low-Drive Product Options
The SL23EP08 is offered with high drive “-1H, -2H and -
5H” and standard drive “-1, -2, -3 and -4” options. These
drive options enable the users to control load levels,
frequency range and EMI control. Refer to the AC
electrical tables for the details.
SL23EP08-5H is offered only with high drive option.
SL23EP08-3 and -4 are offered only with standard drive
option.
Skew and Zero Delay
All outputs should drive the similar load to achieve
output-to-output skew and input-to-output delay
specifications given in the AC electrical tables. However,
zero-delay between input and outputs can be adjusted by
changing the loading of FBK pin relative to the banks A
and B clocks since FBK is the feedback to the PLL.
Power Supply Range (VDD)
The SL23EP08 is designed to operate with from 3.3V to
2.5V VDD power supply range. An internal on-chip
voltage regulator is used to provide PLL constant power
supply of 1.8V, leading to a consistent and stable PLL
electrical performance in terms of skew, jitter and power
dissipation. The SL23EP08 I/O is powered by using
VDD.