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参数资料
| 型号： | SL23EP09ZI-1HT |
| 元件分类： | 时钟及定时 |
| 英文描述： | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 4.40 MM, ROHS COMPLIANT, TSSOP-16 |
| 文件页数： | 11/13页 |
| 文件大小： | 288K |
| 代理商： | SL23EP09ZI-1HT |
Rev 1.1, February 2, 2007
Page 7 of 13
SL23EP09
AC Electrical Specifications (VDD=3.3V and 2.5V)
Symbol
Description
Condition
Min
Typ
Max
Unit
3.3V High Drive
10
–
220
MHz
3.3V Standard Drive
10
–
167
MHz
2.5V High Drive
10
–
200
MHz
FMAX
Maximum Frequency
[1]
(Input=Output )
2.5V Standard Drive
10
–
133
MHz
<135 MHz, VDD=3.3V
25
–
75
%
INDC
Input Duty Cycle
<135 MHz, VDD=2.5V
40
–
60
%
<135 MHz, VDD=3.3V
47
–
53
%
OUTDC
Output Duty Cycle
[2]
<135 MHz, VDD=2.5V
45
55
%
Std drive, CL = 30 pF, <100 MHz
–
1.6
ns
Std drive, CL = 22 pF, <135 MHz
–
1.6
ns
Std drive, CL = 15 pF, <170 MHz
–
0.6
ns
High drive, CL = 30 pF, <100 MHz
–
1.2
ns
High drive, CL = 22 pF, <135 MHz
–
1.2
ns
tr/f3.3
Rise, Fall Time (3.3V)
[2]
(Measured at: 0.8 to 2.0V)
High drive, CL = 15 pF, >135 MHz
–
0.5
ns
Std drive, CL = 15 pF, <135 MHz
–
1.5
ns
High drive, CL = 30 pF, <100 MHz
–
2.1
ns
High drive, CL = 22 pF, <135 MHz
–
1.3
ns
tr/f2.5
Rise, Fall Time (2.5)
[2]
(Measured at: 0.6 to 1.8V)
High drive, CL = 15 pF, >135 MHz
–
1.2
ns
All outputs CL=0, 3.3V supply, 2.5 power
supply, standard drive
–
45
100
ps
t1
Output-to-Output Skew [9]
(Measured at VDD/2)
All outputs CL=0, 2.5V power supply, high
drive
–
110
ps
PLL Bypass mode
1.5
–
4.4
ns
PLL enabled @ 3.3V
–100
–
100
ps
t2
Delay Time, CLKIN Rising
Edge to CLKOUT Rising
Edge
[2]
(Measured at VDD/2)
PLL enabled @2.5V
–200
–
200
ps
Measured at VDD/2. Any output to any
output, 3.3V supply
–
±150
ps
t3
Part-to-Part Skew
[2]
(Measured at VDD/2)
Measured at VDD/2. Any output to any
output, 2.5V supply
–
±300
ps
Notes:
1. For the given maximum loading conditions. See CL in Operating Conditions Table.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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