参数资料
型号: SL23EP09ZI-1T
元件分类: 时钟及定时
英文描述: 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封装: 4.40 MM, ROHS COMPLIANT, TSSOP-16
文件页数: 13/13页
文件大小: 288K
代理商: SL23EP09ZI-1T
Rev 1.1, February 2, 2007
Page 9 of 13
SL23EP09
External Components & Design Considerations
Typical Application Schematic
Comments and Recommendations
Decoupling Capacitor:
A decoupling capacitor of 0.1μF must be used between VDD and VSS pins. Place the capacitor on
the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via
should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin.
Series Termination Resistor
: A series termination resistor is recommended if the distance between the output clocks and
the load is over 1 inch. The nominal impedance of the clock outputs is given on the page 4. Place the series termination
resistors as close to the clock outputs as possible.
Zero Delay and Skew Control:
All outputs and CLKIN pins should be loaded with the same load to achieve “Zero Delay”
between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for feedback to PLL, and
sees an additional 2 pF load with respect to Bank A and B clocks. For applications requiring zero input/output delay, the load
at the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the capacitance at
the CLKOUT pin could be increased or decreased to increase or decrease the delay between Bank A and B clocks and
CLKIN.
For minimum pin-to-pin skew, the external load at all the Bank A and B clocks must be the same.
相关PDF资料
PDF描述
SL28505ALCT PROC SPECIFIC CLOCK GENERATOR, QCC64
SL28505ALC PROC SPECIFIC CLOCK GENERATOR, QCC64
SL28506BZC-2T 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
SL28506BOC-2 PROC SPECIFIC CLOCK GENERATOR, PDSO56
SL28506BZIT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64
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