参数资料
型号: SL28504RLCT
厂商: SILICON LABORATORIES
元件分类: 时钟产生/分配
英文描述: OTHER CLOCK GENERATOR, QCC64
封装: 9 X 9 MM, LEAD FREE, MO-220, QFN-64
文件页数: 26/31页
文件大小: 325K
代理商: SL28504RLCT
SL28504
ADVANCE
INFORMATION
Rev 1.1
Page 4 of 31
64-QFN Pin Definitions
49
VDD_CPU_IO
PWR
3.3V-1.05V power supply for CPU outputs.
50
CPU1#
O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2.
51
CPU1
O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2.
52
VSS_CPU
GND
Ground for outputs.
53
CPU0#
O, DIF Differential CPU clock outputs.
54
CPU0
O, DIF Differential CPU clock outputs.
55
VDD_CPU
PWR
3.3V Power supply for CPU PLL.
56
CK_PWRGD/PWRDWN#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, and ITP_EN.
After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
57
FSB/TEST_MODE
I
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
58
VSS_REF
GND
Ground for outputs.
59
XTAL_OUT
O, SE 14.318 MHz Crystal output.
60
XTAL_IN
I
14.318 MHz Crystal input.
61
VDD_REF
PWR
3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
62
REF0/FSC/TEST_SEL
I/O
3.3V tolerant input for CPU frequency selection/fixed 14.318 clock output. Selects
test mode if pulled to VIHFS_C when CK_PWRGD is asserted HIGH. Refer to DC
Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifications.
63
SMB_DATA
I/O
SMBus compatible SDATA.
64
SMB_CLK
I
SMBus compatible SCLOCK.
64-TSSOP Pin Definitions
Pin No.
Name
Type
Description
Pin No.
Name
Type
Description
1
VSS_REF
GND
Ground for outputs.
2
XTAL_OUT
O, SE 14.318 MHz Crystal output.
3
XTAL_IN
I
14.318 MHz Crystal input.
4
VDD_REF
PWR
3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
5
REF0/FSC/TEST_SEL
I/O
3.3V tolerant input for CPU frequency selection/fixed 14.318 clock output. Selects
test mode if pulled to VIHFS_C when CK_PWRGD is asserted HIGH. Refer to DC
Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifications.
6
SMB_DATA
I/O
SMBus compatible SDATA.
7
SMB_CLK
I
SMBus compatible SCLOCK.
8
PCI_0
O, SE 33 MHz clock
9
VDD_PCI
PWR
3.3V Power supply for PCI PLL.
10
PCI_1
O, SE 33 MHz clock
11
PCI_2
O, SE 33 MHz clock.
12
PCI_3
I/O, SE, 3.3V tolerant input for CPU frequency selection/33 MHz clock.
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