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| 型号： | SL28506BOC-2 |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | ROHS COMPLIANT, SSOP-56 |
| 文件页数： | 6/28页 |
| 文件大小： | 337K |
| 代理商： | SL28506BOC-2 |
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SL28506-2
Rev 1.3 June 18, 2008
Page 14 of 28
PD Assertion
When PS is sampled HIGH by two consecutive rising edges of
CPUC, all single-ended outputs will be held LOW on their next
HIGH-to-LOW transition and differential clocks must held
LOW. In the event that PD mode is desired as the initial
power-on state, PD must be asserted HIGH in less than 10 s
after asserting CK_PWRGD.
PD# Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300 s of PD# deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Below is an example showing the relationship of
clocks coming up.
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used to
synchronously stop and start the CPU output clocks while the
rest of the clock generator continues to function. When the
CPU_STP# pin is asserted, all CPU outputs that are set with
the SMBus configuration to be stoppable via assertion of
CPU_STP# are stopped within two to six CPU clock periods
after being sampled by two rising edges of the internal CPUC
clock. The final states of the stopped CPU signals are CPUT
= HIGH and CPUC = LOW.
PD#
USB, 48MHz
DOT96T
DOT96C
SRCT 100MHz
SRCC 100MHz
CPUT, 133MHz
PCI, 33 MHz
REF
CPUC, 133MHz
Figure 3. PD Assertion Timing Waveform
DOT96C
PD#
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
USB, 48MHz
DOT96T
SRCT 100MHz
Tstable
<1.8ms
PCI, 33MHz
REF
Tdrive_PW RDN#
<300S, >200mV
PD Deassertion Timing Waveform
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SL28506BZC | 功能描述:时钟发生器及支持产品 CK505 v1.1 PCIe Gen2 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28506BZC-2 | 功能描述:时钟发生器及支持产品 CK505 v1.1 PCIe Gen2 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28506BZC-2T | 功能描述:时钟发生器及支持产品 CK505 v1.1 PCIe Gen2 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28506BZCT | 功能描述:时钟发生器及支持产品 CK505 v1.1 PCIe Gen2 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28506BZI | 功能描述:时钟发生器及支持产品 CK505 v1.1 PCIe Gen2 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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