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| 型号： | SL28541BZC-2T |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 6/28页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CK505 MOBILE 56TSSOP |
| 标准包装： | 2,000 |
| 类型： | 时钟/频率发生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服务器 |
| 输入： | 时钟，晶体 |
| 输出： | HCSL，LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:21 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 400MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
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SL28541-2
...................... DOC #: SP-AP-0064 (Rev. AB) Page 14 of 28
Calculating Load Capacitors
In addition to the standard external trim capacitors, consider
the trace capacitance and pin capacitance to calculate the
crystal loading correctly. Again, the capacitance on each side
is in series with the crystal. The total capacitance on both side
is twice the specified crystal load capacitance (CL). Trim
capacitors are calculated to provide equal capacitive loading
on both sides.
,
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs ............................................. Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires, etc.)
Dial-A-Frequency (CPU and SRC Clocks)
This feature allows the user to over-clock their system by
slowly stepping up the CPU or SRC frequency. When the
programmable output frequency feature is enabled, the CPU
and SRC frequencies are determined by the following
equation:
Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M.
“N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
“G” stands for the PLL Gear Constant, which is determined
by the programmed value of FS[E:A]. See Table 1,
Frequency Select Table for the Gear Constant for each
Frequency selection. The PCI Express only allows user
control of the N register, the M value is fixed and
documented in Table 1, Frequency Select Table.
In this mode, the user writes the desired N and M values into
the DAF I2C registers. The user cannot change only the M
value and must change both the M and the N values at the
same time, if they require a change to the M value. The user
may change only the N value.
Associated Register Bits
CPU_DAF Enable – This bit enables CPU DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the CPU_DAF_N
register. Note that the CPU_DAF_N and M register must
contain valid values before CPU_DAF is set. Default = 0,
(No DAF).
CPU_DAF_N – There are nine bits (for 512 values) to
linearly change the CPU frequency (limited by VCO range).
Default = 0, (0000). The allowable values for N are detailed
in Table 1, Frequency Select Table.
CPU DAF M – There are 7 bits (for 128 values) to linearly
change the CPU frequency (limited by VCO range). Default
= 0, the allowable values for M are detailed in Table 1,
Frequency Select Table
SRC_DAF Enable – This bit enables SRC DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the SRC_DAF_N
register. Note that the SRC_DAF_N register must contain
valid values before SRC_DAF is set. Default = 0, (No DAF).
SRC_DAF_N – There are nine bits (for 512 values) to
linearly change the CPU frequency (limited by VCO range).
Default = 0, (0000). The allowable values for N are detailed
in Table 1, Frequency Select Table.
Smooth Switching
The device contains one smooth switch circuit that is shared
by the CPU PLL and SRC PLL. The smooth switch circuit
ensures that when the output frequency changes by
overclocking, the transition from the old frequency to the new
frequency is a slow, smooth transition containing no glitches.
The rate of change of output frequency when using the smooth
switch circuit is less than 1 MHz/0.667
s. The frequency
overshoot and undershoot is less than 2%.
The Smooth Switch circuit assigns auto or manual. In Auto
mode, clock generator assigns smooth switch automatically
when the PLL does overclocking. For manual mode, assign
Figure 1. Crystal Capacitive Clarification
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
()
1
=
CLe
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SL28541BZCT | 功能描述:时钟发生器及支持产品 Montevina RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28541BZI | 功能描述:时钟发生器及支持产品 Montevina RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28541BZI-2 | 功能描述:时钟发生器及支持产品 Montevina, Atom RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28541BZI-2T | 功能描述:时钟发生器及支持产品 Montevina, Atom RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28541BZIT | 功能描述:时钟发生器及支持产品 Montevina RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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