参数资料
型号: SL28541BZI-2T
厂商: Silicon Laboratories Inc
文件页数: 22/28页
文件大小: 0K
描述: IC CLOCK CK505 MOBILE 56TSSOP
标准包装: 2,000
类型: 时钟/频率发生器
PLL:
主要目的: Intel CPU 服务器
输入: 时钟,晶体
输出: HCSL,LVCMOS
电路数: 1
比率 - 输入:输出: 1:21
差分 - 输入:输出: 无/是
频率 - 最大: 400MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: *
封装/外壳: *
供应商设备封装: *
包装: *
SL28541-2
........................ DOC #: SP-AP-0064 (Rev. AB) Page 3 of 28
27
SRC4
O, DIF 100MHz Differential serial reference clocks.
28
SRC4#
O, DIF 100MHz Differential serial reference clocks.
29
CPU_STP#
I
3.3V tolerant input for stopping CPU outputs
30
PCI_STP#
I
3.3V tolerant input for stopping PCI and SRC outputs
31
VDD_SRC
PWR
3.3V Power supply for SRC PLL.
32
SRC6#
O, DIF 100MHz Differential serial reference clocks.
33
SRC6
O, DIF 100MHz Differential serial reference clocks.
34
VSS_SRC
GND
Ground for outputs.
35
SRC7#/OE#_6
I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#6 Input controlling SRC6.
(Default SRC7, 100MHz clock).
36
SRC7/OE#_8
I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8.
(Default SRC7, 100MHz clock).
37
VDD_SRC_IO
PWR
0.7V power supply for SRC outputs.
38
SRC8#/CPU2#_ITP#
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
39
SRC8/CPU2_ITP
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
40
NC
No Connect
41
VDD_CPU_IO
PWR
IO Power supply for CPU outputs.
42
CPU1#
O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2)
43
CPU1
O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2)
44
VSS_CPU
GND
Ground for outputs.
45
CPU#0
O, DIF Differential CPU clock outputs.
46
CPU0
O, DIF Differential CPU clock outputs.
47
VDD_CPU
PWR
3.3V Power supply for CPU PLL.
48
CKPWRGD/PD#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, FS_D, SRC5_SEL, and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
49
FSB/TEST_MODE
I
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
50
VSS_REF
GND
Ground for outputs.
51
XOUT
O, SE 14.318MHz Crystal output. (Float XOUT if using CLKIN)
52
XIN/CLKIN
I
14.318MHz Crystal input or 3.3V, 14.318MHz input clock signal.
53
VDD_REF
PWR
3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
54
REF0/FSC/TEST_SEL
I/O
3.3V tolerant input for CPU frequency selection/fixed 14.318MHz clock output.
Selects test mode if pulled to VIHFS_C when CKPWRGD is asserted HIGH. Refer
to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifications.
55
SMB_DATA
I/O
SMBus compatible SDATA.
56 TSSOP Pin Definition (continued)
Pin No.
Name
Type
Description
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