参数资料
型号: SL28641ZXC
元件分类: 时钟产生/分配
英文描述: OTHER CLOCK GENERATOR, PDSO64
封装: 6 X 17 MM, LEAD FREE, TSSOP-64
文件页数: 3/40页
文件大小: 398K
代理商: SL28641ZXC
SL28641/
SL28641-2
PRELIMINARY
CONFIDENTIAL
Rev 1.4
Page 11 of 40
32
VDD_SRC_IO
PWR
3.3V-1.05V power supply for SRC outputs.
33
SRC4
O, DIF 100 MHz Differential serial reference clocks.
34
SRC4#
O, DIF 100 MHz Differential serial reference clocks.
35
SRC11#/OE#_9
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#9 Input controlling SRC9
Default SRC11.
36
SRC11/OE#_10
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#10 Input controlling SRC10.
Default SRC11.
37
CPU_STOP#
I/O,
Dif
3.3V tolerant input for stopping CPU outputs.
38
PCI_STOP#
I/O,
Dif
3.3V tolerant input for stopping PCI and SRC outputs.
39
VDD_SRC
PWR
3.3V Power supply for SRC PLL.
40
VSS_SRC
GND
Ground for outputs.
41
SRC7#/OE#_6
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#6 Input controlling SRC6.
Default SRC7.
42
SRC7/OE#_8
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8.
Default SRC7.
43
VDD_SRC_IO
PWR
3.3V-1.05V power supply for SRC outputs.
44
SRC8#/CPUC2_ITP#
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2.
45
SRC8/CPUT2_ITP
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2.
46
NC
No Connect
47
VDD_CPU_IO
PWR
3.3V-1.05V power supply for CPU outputs.
48
CPU1#
O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2.
49
CPU1
O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2.
50
VSS_CPU
GND
Ground for outputs.
51
CPU#0
O, DIF Differential CPU clock outputs.
52
CPU0
O, DIF Differential CPU clock outputs.
53
VDD_CPU
PWR
3.3V Power supply for CPU PLL.
54
CK_PWRGD/PWRDWN#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, and ITP_EN.
After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
55
FSB/TEST_MODE
I
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
56
VSS_REF
GND
Ground for outputs.
Pin No.
Name
Type
Description
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