参数资料
型号: SL28748ELCT
厂商: Silicon Laboratories Inc
文件页数: 12/19页
文件大小: 0K
描述: IC CLOCK CALPELLA CK505 32QFN
标准包装: 2,500
系列: EProClock®
类型: 时钟/频率发生器,多路复用器
PLL:
主要目的: Intel CPU 服务器
输入: 晶体
输出: HCSL,LVCMOS
电路数: 1
比率 - 输入:输出: 1:8
差分 - 输入:输出: 无/是
频率 - 最大: 133MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 85°C
安装类型: *
封装/外壳: *
供应商设备封装: *
包装: *
SL28748
DOC#: SP-AP-0017 (Rev. AA)
Page 2 of 19
32-QFN Pin Definitions
Pin No.
Name
Type
Description
1
VDD_DOT
PWR 3.3V Power supply for outputs and PLL
2
VSS_DOT
GND
Ground for outputs
3
DOT96
O, DIF Fixed true 96MHz clock output
4
DOT96#
O, DIF Fixed complement 96MHz clock output
5
VDD_27
PWR 3.3V Power supply for 27MHz PLL
6
27M_NSS
O,SE Non-spread 27MHz video clock output
7
27M_SS
O, SE Spread 27MHz video clock output
8
VSS_27
GND
Ground for 27MHz PLL
9
VSS_SATA
GND
Ground for outputs
10
SRC0 / SATA
O, DIF 100MHz True differential serial reference clock
11
SRC0# / SATA#
O, DIF 100MHz Complement differential serial reference clock
12
VSS_SRC
GND
Ground for PLL
13
SRC1
O, DIF 100MHz True differential serial reference clock
14
SRC1#
O, DIF 100MHz Complement differential serial reference clock
15
VDD_SRC_IO
PWR Scalable 3.3V to 1.05V power supply for output buffer
16
CPU_STP#
I
3.3V tolerance input to stop the CPU clock
17
VDD_SRC
PWR 3.3V Power supply for PLL
18
VDD_CPU_IO
PWR Scalable 3.3V to 1.05V power supply for output buffer
19
CPU1#
O, DIF Complement differential CPU clock output
20
CPU1
O, DIF True differential CPU clock output
21
VSS_CPU
GND
Ground for PLL
22
CPU0#
O, DIF Complement differential CPU clock output
23
CPU0
O, DIF True differential CPU clock output
24
VDD_CPU
PWR 3.3V Power supply for CPU PLL
25
CKPWRGD/PD#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW)
26
VSS_REF
GND
Ground for outputs
27
XOUT
O, SE 14.318MHz Crystal output
28
XIN
I
14.318MHz Crystal input
29
VDD_REF
PWR 3.3V Power supply for outputs and also maintains SMBUS registers during
power-down
30
REF/FS**
PD, I/O 3.3V tolerant input for Graphic clock selection/fixed 14.318MHz clock output.
(Internal 100K-ohm pull-down resistor on FS pin)
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
31
SDATA
I/O
SMBus compatible SDATA
32
SCLK
I
SMBus compatible SCLOCK
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