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| 型号： | SL28779ELIT |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 3/22页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CALPELLA CK505 32QFN |
| 标准包装： | 2,500 |
| 系列： | EProClock® |
| 类型： | 时钟/频率发生器，多路复用器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服务器 |
| 输入： | 晶体 |
| 输出： | HCSL，LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:9 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 133MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
SL28779
DOC#: SP-AP-0066 (Rev. AA)
Page 11 of 22
,
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs ............................................. Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires, etc.)
PD# (Power down) Clarification
The CKPWRGD/PD# pin is a dual-function pin. During initial
power up, the pin functions as CKPWRGD. Once CKPWRGD
has been sampled HIGH by the clock chip, the pin assumes
PD# functionality. The PD# pin is an asynchronous active
LOW input used to shut off all clocks cleanly before shutting
off power to the device. This signal is synchronized internally
to the device before powering down the clock synthesizer. PD#
is also an asynchronous input for powering up the system.
When PD# is asserted LOW, clocks are driven to a LOW value
and held before turning off the VCOs and the crystal oscillator.
PD# (Power down) Assertion
When PD# is sampled LOW by two consecutive rising edges
of CPU clocks, all single-ended outputs will be held LOW on
their next HIGH-to-LOW transition and differential clocks must
held LOW. When PD# mode is desired as the initial power on
state, PD# must be asserted LOW in less than 10
s after
asserting CKPWRGD.
PD# Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from are driven high in less than 300
s of
PD# deassertion to a voltage greater than 200 mV. After the
clock chip’s internal PLL is powered up and locked, all outputs
are enabled within a few clock cycles of each clock. Figure 4
is an example showing the relationship of clocks coming up.
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
(
)
1
=
CLe
Figure 3. Power Down Assertion Timing Waveform
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