参数资料
型号: SL28EB717ALI
厂商: Silicon Laboratories Inc
文件页数: 2/22页
文件大小: 0K
描述: IC CLK CK505 TNLCRK/TOPCLF 48QFN
标准包装: 490
系列: EProClock®
类型: 时钟/频率发生器,多路复用器
PLL:
主要目的: Intel CPU 服务器
输入: 时钟,晶体
输出: HCSL,LVCMOS
电路数: 1
比率 - 输入:输出: 1:13
差分 - 输入:输出: 无/是
频率 - 最大: 166.67MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: *
封装/外壳: *
供应商设备封装: *
包装: *
SL28EB717
DOC#: SP-AP-0755 (Rev. AA)
Page 10 of 22
Byte 14: Control Register 14
.
PD# (Power down) Clarification
The CKPWRGD/PD# pin is a dual-function pin. During initial
power up, the pin functions as CKPWRGD. Once CKPWRGD
has been sampled HIGH by the clock chip, the pin assumes
PD# functionality. The PD# pin is an asynchronous active
LOW input used to shut off all clocks cleanly before shutting
off power to the device. This signal is synchronized internally
to the device before powering down the clock synthesizer. PD#
is also an asynchronous input for powering up the system.
When PD# is asserted LOW, clocks are driven to a LOW value
and held before turning off the VCOs and the crystal oscillator.
PD# (Power down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must held
LOW. When PD mode is desired as the initial power on state,
PD must be asserted HIGH in less than 10
s after asserting
CKPWRGD.
PD# Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from power down are driven high in less
than 300
s of PD# deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are enabled within a few clock cycles of
each clock. Figure 2 is an example showing the relationship of
clocks coming up.
Bit
@Pup
Name
Description
7
1
RESERVED
6
0
RESERVED
5
1
RESERVED
40
OTP_4
OTP_ID
Idenification for programmed device
30
OTP_3
20
OTP_2
10
OTP_1
00
OTP_0
Table 4. Output Driver Status during CPU_STP# & PCIS_STP#
CPU_STP#
Asserted
PCI_STP#
Asserted
CLKREQ#
Asserted
SMBus OE Disabled
Single-ended Clocks
Stoppable
Running
Driven Low
Running
Driven low
Non stoppable
Running
Differential Clocks
Stoppable
Clock driven high
Clock driven low
Clock# driven low
Non stoppable
Running
Table 5. Output Driver Status
All Single-ended Clocks
All Differential Clocks
w/o Strap
w/ Strap
Clock
Clock#
PD# = 0 (Power down)
Low
Hi-z
Low
相关PDF资料
PDF描述
SL28EB719AZI IC CLK CK505 TNLCK/TPCLF 48TSSOP
SL28EB740AZI IC CLK CK505 TNLCK/TPCLF 56TSSOP
SL28PCIE10ALI IC CLOCK PCIE GEN2 4CH 32QFN
SL28PCIE14ALIT IC CLOCK PCIE GEN2/3 BUFF 32QFN
SM3-19.44M IC MOD TIMING 19.440MHZ STATUM 3
相关代理商/技术参数
参数描述
SL28EB717ALIT 功能描述:时钟发生器及支持产品 Tunnel Creek Queen’s Bay platform RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56
SL28EB719AZI 功能描述:时钟发生器及支持产品 Tunnel Creek Queen’s Bay platform RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56
SL28EB719AZIT 功能描述:时钟发生器及支持产品 Tunnel Creek Queen’s Bay platform RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56
SL28EB733ALI 制造商:Silicon Laboratories Inc 功能描述:4 OUTPUT PCI EXPRESS (PCIE) GEN1/2 WITH 25MHZ AND 33MHZ LVCM - Bulk 制造商:Silicon Laboratories Inc 功能描述:IC EMB CLOCK GENERATOR 32QFN
SL28EB733ALIT 制造商:Silicon Laboratories Inc 功能描述:4 OUTPUT PCI EXPRESS (PCIE) GEN1/2 WITH 25MHZ AND 33MHZ LVCM - Tape and Reel 制造商:Silicon Laboratories Inc 功能描述:IC EMB CLOCK GENERATOR 32QFN